US5777501A
Expired / Lapsed
US
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Digital delay line for a reduced jitter digital delay lock loop
Assignee: Mosaid Technologies Inc
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Filing: 1996-04-29
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Granted: 1998-07-07
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Expires: 2016-04-29
Abstract
Abstract A delay line having variable delay comprising apparatus for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected inverter stages each for receiving and translating the inverted and non-inverted versions of the input clock signal, inverted and non-inverted outputs of each of the inverter stages except a last inverter stage in series being cross-connected to inputs of an immediately following inverter stage, and apparatus for shunting outputs of one of the inverter stages to a pair of output nodes.
Inventors
- 👤 Maamoun AbouSeido
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:48
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
131 words
A digital delay line having variable delay comprising means for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected delay cells each comprised of a pair of inverters, each delay cell having a fixed delay and providing an inverted and a non-inverted output, a first delay cell for receiving and translating the inverted and non-inverted versions of the input clock signal, successive delay cells each receiving and translating the inverted and non-inverted output of a preceding stage, inverted and non-inverted outputs of each of the delay cells except a last delay cell in said plurality being directly cross-connected to inputs of an immediately following delay cell, and means for shunting outputs of a delay cell to a pair of output nodes.
Claim 2
Dependent Claim
131 words
A digital delay line having variable delay comprising means for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected delay cells each comprised of a pair of inverters, each delay cell having a fixed delay and providing an inverted and a non-inverted output, a first delay cell for receiving and translating the inverted and non-inverted versions of the input clock signal, successive delay cells each receiving and translating the inverted and non-inverted output of a preceding stage, inverted and non-inverted outputs of each of the delay cells except a last delay cell in said plurality being directly cross-connected to inputs of an immediately following delay cell, and means for shunting outputs of a delay cell to a pair of output nodes.
Claim 3
Dependent Claim
133 words
A delay line having variable delay comprising a plurality of serially connected delay cells, each delay cell having a fixed delay, each delay cell comprising a single inverter stage formed of a first inverter and a second inverter, an input of said first inverter of a first delay sell being connected to an input line carrying a clock signal and an input of said second inverter of said first delay cell being connected to an input line carrying an inverted clock signal, outputs of each delay cell except a last delay cell being crosscoupled to input terminals of a respectively immediately following delay cell, and means for shunting outputs of said first and second inverters of one of the delay cells to an output buffer for provision of opposite logic level output signals.
Claim 4
Dependent Claim
133 words
A delay line having variable delay comprising a plurality of serially connected delay cells, each delay cell having a fixed delay, each delay cell comprising a single inverter stage formed of a first inverter and a second inverter, an input of said first inverter of a first delay sell being connected to an input line carrying a clock signal and an input of said second inverter of said first delay cell being connected to an input line carrying an inverted clock signal, outputs of each delay cell except a last delay cell being crosscoupled to input terminals of a respectively immediately following delay cell, and means for shunting outputs of said first and second inverters of one of the delay cells to an output buffer for provision of opposite logic level output signals.
Claim 5
Dependent Claim
137 words
A delay line as defined in claim 1 in which each delay cell is further comprised of two pairs of FETs having their sources and drains connected in series, one serially connected pair of FETs being connected between an output of a first inverter of the pair of inverters and ground, and the other serially connected pair of FETs being connected between an output of a second inverter of the pair of inverters and ground, means for providing a control input to each of the pair of inverters and to the gates of the FETs connected to ground, the output of said first inverter being connected to the gate of a FET connected to the second inverter, and the output of said second inverter being connected to the gate of a FET connected to the first inverter.
References Cited (Backward Citations)
US4506167A
Cited
US4494021A
Cited
US4820944A
Cited
US4797586A
Cited
JPH0242814A
Cited
US5173870A
Cited
US5012142A
Cited
JPH03211914A
Cited
US5057701A
Cited
US5144174A
Cited
US5220206A
Cited
US5243240A
Cited
US5596610A
Cited
US5497115A
Cited
US5508648A
Cited
US5581207A
Cited
US5565817A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |