Semiconductor integrated circuit

Abstract

Abstract PURPOSE:To obtain complementary double-phase signal to accompany same time delay in both output sides by connecting two inverters across between the output side of an even number of inverters and the output side of an odd number of inverters. CONSTITUTION:After a node N11 goes to be L, a node N14 tries to be L H after a delay time tau24 of an inverter 24, however, it can be H by the influence of an inverter 26. On the other hand, after the node N11 goes to be L, a node N13 tries to be H L after delay times tau22+tau23 of inverters 22 and 23. At such a time, since N14 tries to be L H preceding to the N13, the output of an inverter 25 next tries to be H L. Thus, the N13 tries to be L earlier than the delay times tau22+tau23 and the operation of the N13 is transmitted to the inverter 26. Then, the output of the inverter 26 goes to be H. Thus, the N14 rapidly goes to be H. Accordingly, in the N13 and 14, the complementary signals of double phases to have the same timing of a signal change appear.

Inventors

• 👤 Kotaro Tanaka
• 👤 幸太郎 田中
• 👤 Makoto Yomo
• 👤 誠 四方
• 👤 Toshihiko Ichioka
• 👤 市岡　俊彦

Bibliographic Details