Integrated circuit with improved interconnect structure and process for making same

Claim 2

A semiconductor device, comprising: a semiconductor die; and an electronic circuit located on said die; and a first via having a first via top portion beginning at a top surface of said die and extending through said die to a first via bottom portion on a bottom surface of said die; and a second via having a second via top portion beginning at said top surface of said die and extending through said die to a second via bottom portion on said bottom surface of said die, said second via being substantially filled with dielectric material adapted to provide support for said semiconductor die; and an input/output (I/O) interconnect physically and electrically coupled to said first via bottom portion, said I/O interconnect structure being located within an area on the bottom surface of said die and further being arranged so as to comprise a portion of a chip scale package integrated with said semiconductor die; and an I/O signal line coupled to said electronic circuit and said I/O interconnect structure by passing through said first via; wherein electrical signals can be communicated through said I/O signal line and said I/O interconnect structure between said electronic circuit and a second semiconductor device, which second semiconductor device is separate from the first semiconductor device.

Claim 3

The device of claim 1 , further including a plurality of additional I/O interconnects, and wherein all of said I/O interconnects are located within a surface area corresponding to the bottom surface of said die.

Claim 4

The device of claim 2 , further wherein said I/O interconnects occupy more than half thin of the bottom surface area of said die.

Claim 5

The device of claim 3 , further wherein said electronic circuit occupies substantially all of said top surface area of said die.

Claim 6

The device of claim 1 , wherein such die is formed such that no I/O interconnects are located on said top surface of said die.

Claim 7

The device of claim 5 , wherein said device is contained within a single semiconductor wafer including a plurality of die for a plurality of additional identical devices, and wherein a top surface of said wafer includes only said plurality of die for such plurality of additional identical devices.

Claim 8

The device of claim 1 , wherein substantially all of said top surface of said die is used for said electronic circuit, and no I/O interconnects are located on said top surface of said die.

Claim 9

The device of claim 1 , further including a plurality of additional I/O interconnects, and wherein a first portion of said plurality of I/O interconnects are located within a surface area corresponding to the bottom surface of said die, and a second portion of said plurality of I/O interconnects are located within a surface area corresponding to the top surface of said die.

Claim 10

The device of claim 1 , wherein said electronic circuit and said I/O interconnects are integrated on opposite sides of a single die.

Claim 11

The device of claim 9 , wherein said top portion and said bottom portion of said first via are different in size.

Claim 12

The device of claim 1 , wherein said first via is filled with a conductive material capable of withstanding a high temperature cycle associated with a manufacturing operation used for said electronic circuit.

Claim 13

The device of claim 11 , wherein said top portion of said via is coupled to a top side conductive pad located on the top side of said die, said top side conductive pad also comprising a portion of said chip scale package integrated with said semiconductor die.

Claim 14

The device of claim 1 , wherein said I/O interconnect is a bottom side conductive pad located on the bottom side of said die.

Claim 15

The device of claim 13 , wherein said top portion of said first via is coupled to a top side conductive pad located on the top side of said die, and wherein said top side conductive pad is smaller than said bottom side conductive pad.

Claim 16

The device of claim 1 , wherein said I/O interconnect includes a conductive bump structure.

Claim 17

The device of claim 1 , wherein said first via is contained in a through-hole that is formed prior to the formation of said first electronic circuit.

Claim 18

A multi-chip electronic circuit, comprising: a first and second semiconductor die; and a first electronic circuit being located on said first die; and a second electronic circuit being located on said second die; and said first semiconductor die including a first via, which first via has a first via top portion beginning at a first top surface of said first die and extending through said first die to a first via bottom portion on a first bottom surface of said first die; said first semiconductor die including a second via having a second via top portion beginning at said top surface of said first die and extending through said die to a second via bottom portion on a bottom surface of said die, said second via being substantially filled with dielectric material adapted to provide support for said first semiconductor die; and a first input/output (I/O) interconnect physically and electrically coupled to said first via bottom portion, said first I/O interconnect structure being located within a first area on the first bottom surface of said first die and further being arranged so as to comprise a portion of a chip scale package integrated with said first semiconductor die; and a first I/O signal line coupled to said first electronic circuit and said first I/O interconnect structure by passing through said first via; a second input/output (I/O) interconnect electrically coupled to said second electronic circuit, and further being physically and electrically coupled to said first I/O interconnect; wherein electrical signals can be communicated between said first and second electronic circuits through said first and second I/O interconnects.

Claim 19

A multi-chip electronic circuit, comprising: a first and second semiconductor die; and a first electronic circuit being located on said first die; and a second electronic circuit being located on said second die; and said first semiconductor die including a first via, which first via has a first via top portion beginning at a first top surface of said first die and extending through said first die to a first via bottom portion on a first bottom surface of said first die; said first semiconductor die including a second via having a second via top portion beginning at said top surface of said first die and extending through said die to a second via bottom portion on a bottom surface of said die, said second via being substantially filled with dielectric material adapted to provide support for said first semiconductor die; and a first input/output (I/O) interconnect physically and electrically coupled to said first via bottom portion, said first I/O interconnect structure being located within a first area on the first bottom surface of said first die and further being arranged so as to comprise a portion of a chip scale package integrated with said first semiconductor die; and a first I/O signal line coupled to said first electronic circuit and said first I/O interconnect structure by passing through said first via; a second input/output (I/O) interconnect electrically coupled to said second electronic circuit, and further being physically and electrically coupled to said first I/O interconnect; wherein electrical signals can be communicated between said first and second electronic circuits through said first and second I/O interconnects.

Claim 20

The circuit of claim 17 , further wherein: said first I/O interconnect includes a first conductive bump structure as part of said chip scale package; said second I/O interconnect includes a second conductive bump structure comprising a portion of a second chip scale package integrated with said second semiconductor die; and further wherein said first and second conductive bumps are joined together to effectuate an electronic signal path.

Claim 21

The circuit of claim 17 , further wherein: said first I/O interconnect includes a conductive bump as part of said chip scale package; said second I/O interconnect includes a bond pad; and further wherein said conductive bump and bond pad are joined together to effectuate an electronic signal path.

Claim 22

The circuit of claim 17 , further wherein said second semiconductor die includes a third via, which third via has a third via top portion beginning at a second top surface of said second die and extending through said second die to a third via bottom portion on a second bottom surface of said second die; and said second input/output (I/O) interconnect is electrically coupled to said third via top portion.

Claim 23

The circuit of claim 20 , further wherein said second semiconductor die includes a third I/O interconnect, which third I/O interconnect is located on said second bottom surface of said second die and is coupled to said third via bottom portion so as to comprise a portion of a second chip scale package integrated with said second semiconductor die.

Claim 24

The circuit of claim 21 , further including: a third semiconductor die; and a third electronic circuit being located on said third die; and a fourth input/output (I/O) interconnect electrically coupled to said third electronic circuit, and further being physically and electrically coupled to said third I/O interconnect; wherein electrical signals can be communicated between said second and third electronic circuits through said third and fourth I/O interconnects.

Claim 25

The multi-chip electronic circuit of claim 17 , wherein said first via is contained in a through-hole that is formed prior to the formation of said first electronic circuit.

Claim 26

A chip scale package for a semiconductor device containing a plurality of electronic circuits, said chip scale package comprising: a semiconductor body having a size and shape configured to accommodate the plurality of electronic circuits in the semiconductor device; and a first via having a first via top portion beginning at a top surface of said body and extending through said die to a first via bottom portion on a bottom surface of said body; and a second via having a second via top portion beginning at said top surface of said body and extending through said body to a second via bottom portion on said bottom surface of said body, said second via being substantially filled with dielectric material adapted to provide support for said semiconductor body; and an input/output (I/O) interconnect physically and electrically coupled to said first via bottom portion, said I/O interconnect structure being located within an area on the bottom surface of said body; and an I/O signal line formed of a conductive material passing through said first via and coupled to said I/O interconnect structure; wherein said packaging for the device is formed prior to the formation of any of the plurality of electronic circuits.

Claim 27

A chip scale package for a semiconductor device containing a plurality of electronic circuits, said chip scale package comprising: a semiconductor body having a size and shape configured to accommodate the plurality of electronic circuits in the semiconductor device; and a first via having a first via top portion beginning at a top surface of said body and extending through said die to a first via bottom portion on a bottom surface of said body; and a second via having a second via top portion beginning at said top surface of said body and extending through said body to a second via bottom portion on said bottom surface of said body, said second via being substantially filled with dielectric material adapted to provide support for said semiconductor body; and an input/output (I/O) interconnect physically and electrically coupled to said first via bottom portion, said I/O interconnect structure being located within an area on the bottom surface of said body; and an I/O signal line formed of a conductive material passing through said first via and coupled to said I/O interconnect structure; wherein said packaging for the device is formed prior to the formation of any of the plurality of electronic circuits.

Claim 28

The package of claim 24 , further including a plurality of additional I/O interconnects, and wherein all of said I/O interconnects are located within a surface area corresponding to the bottom surface of said body.

Claim 29

The package of claim wherein said electronic circuit and said I/O interconnects can be formed on opposite sides of said semiconductor body.

Claim 30

The package of claim 24 , wherein said package is contained within a single semiconductor wafer including a plurality of additional identical packages for a corresponding plurality of die formed in said single semiconductor wafer.

Claim 31

The package of claim 22 , wherein said first via is filled with a conductive material capable of withstanding a high temperature cycle associated with a manufacturing operation used for said electronic circuit.

Claim 32

The package of claim 24 , wherein said first top portion of said first via is coupled to a top side conductive pad located on the top side of said body.

Claim 33

The package of claim 24 , wherein said I/O interconnect is a bottom side conductive pad located on the bottom side of said body.

Claim 34

The package of claim 30 , wherein said first top portion of said first via is coupled to a top side conductive pad located on the top side of said body, and wherein said top side conductive pad is smaller than said bottom side conductive pad.

Claim 35

The package of claim 24 , herein said I/O interconnect includes a conductive bump structure.

Claim 36

The package of claim 24 , wherein said second via is filled with a dielectric material adapted for providing structural support to a wafer containing such semiconductor body during a manufacturing operation associated with said plurality of electronic circuits.

Claim 37

A semiconductor device, comprising: a semiconductor die; and an electronic circuit located on said die; and a via having a via top portion beginning at a top surface of said die and extending through said die to a via bottom portion on a bottom surface of said die, wherein said via top portion and said via bottom portion are different in size; and an input/output (I/O) interconnect physically and electrically coupled to said via bottom portion, said I/O interconnect structure including a bottom side conductive pad located within an area on the bottom surface of said die such that said electronic circuit and said I/O interconnects are integrated on opposite sides of said semiconductor die; and an I/O signal line coupled to said electronic circuit and said I/O interconnect structure by passing through said via; wherein electrical signals can be communicated through said I/O signal line and said I/O interconnect structure between said electronic circuit and a second semiconductor device, which second semiconductor device is separate from the first semiconductor device; and further wherein said top portion of said via is coupled to a top side conductive pad located on said top surface of said die, and wherein said top side conductive pad is smaller than said bottom side conductive pad.

Claim 38

A semiconductor device, comprising: a semiconductor die; and an electronic circuit located on said die; and a via having a via top portion beginning at a top surface of said die and extending through said die to a via bottom portion on a bottom surface of said die, wherein said via top portion and said via bottom portion are different in size; and an input/output (I/O) interconnect physically and electrically coupled to said via bottom portion, said I/O interconnect structure including a bottom side conductive pad located within an area on the bottom surface of said die such that said electronic circuit and said I/O interconnects are integrated on opposite sides of said semiconductor die; and an I/O signal line coupled to said electronic circuit and said I/O interconnect structure by passing through said via; wherein electrical signals can be communicated through said I/O signal line and said I/O interconnect structure between said electronic circuit and a second semiconductor device, which second semiconductor device is separate from the first semiconductor device; and further wherein said top portion of said via is coupled to a top side conductive pad located on said top surface of said die, and wherein said top side conductive pad is smaller than said bottom side conductive pad.

Claim 39

The device of claim 34 , further including a plurality of additional I/O interconnects, and wherein all of said I/O interconnects are located within a surface area corresponding to the bottom surface of said die.

Claim 40

The device of claim 35 , further wherein said I/O interconnects occupy more than half of the bottom surface area of said die.

Claim 41

The device of claim 36 , further wherein said electronic circuit occupies substantially all of said top surface area of said die.

Claim 42

The device of claim 34 , wherein such die is formed such that no I/O interconnects are located on said top surface of said die.

Claim 43

The device of claim 34 , wherein substantially all of said top surface of said die is used for said electronic circuit, and no I/O interconnects are located on said top surface of said die.

Claim 44

The device of claim 34 , further including a plurality of additional I/O interconnects, and wherein a first portion of said plurality of I/O interconnects are located within a surface area corresponding to the bottom surface of said die, and a second portion of said plurality of I/O interconnects are located within a surface area corresponding to the top surface of said die.

Claim 45

The device of claim 34 , wherein said electronic circuit and said I/O interconnects are integrated on opposite sides of a single die.

Claim 46

The device of claim 38 , wherein said device is contained within a single semiconductor wafer including a plurality of die for a plurality of additional identical devices, and wherein a top surface of said wafer includes only said plurality of die for such plurality of additional identical devices.

Claim 47

The device of claim 34 , wherein said via is filled with conductive material.

Claim 48

The device of claim 43 , wherein said top portion of said via is coupled to a top side conductive pad located on said top surface of said die.

Claim 49

The device of claim 34 , wherein said I/O interconnect includes a conductive bump structure.