US5424245A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming vias through two-sided substrate
Assignee: NXP USA Inc
•
Filing: 1994-01-04
•
Granted: 1995-06-13
•
Expires: 2014-01-04
Abstract
Abstract An integrated circuit substrate (26) is formed with active circuit elements (24, 32) on first and second surfaces of the substrate. The active circuit elements are interconnected with though-substrate vias (28) to minimize signal routing and reduce propagation delay. The through-substrate vias may be formed with a plurality of holes (52) through the IC substrate. A dielectric layer (54) is deposited on the surface of the IC substrate and through the holes. A conductive layer (56) is deposited through the holes to form the through-substrate vias. The dielectric layer is removed from the surface of the IC substrate to leave the through-substrate vias isolated from the IC substrate by the dielectric layer. A second substrate (26) is formed as described and the two substrates are joined as a two-sided chip (21) with active circuit elements on both sides interconnected by through-substrate vias.
Inventors
- 👤 Richard W. Gurtler
- 👤 Jeffrey Pearse
- 👤 Syd R. Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0242; H10W20/20; H10W72/00; H10W72/20; H10W72/221; H10W72/227; H10W72/241; H10W72/242; H10W72/247; H10W72/248; H10W72/29; H10W72/851; H10W72/853; H10W72/856; H10W72/90; H10W72/941; H10W72/942; H10W90/00; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
A method of forming through-substrate vias in a substrate, comprising the steps of: forming a first hollow region through a first substrate; depositing a first dielectric layer on a first surface of said first substrate and on inner surfaces of said first hollow region; depositing a first conductive layer through said first hollow region to form a first through-substrate via; removing said first conductive layer and said first dielectric layer from said first surface of said first substrate to leave said first through-substrate via isolated from said first substrate by said first dielectric layer; forming a first IC device layer on said first surface of said first substrate with circuit nodes electrically coupled to the through-substrate vias; forming a first interconnect layer on said first IC device layer; forming first inter-chip interconnects on said first interconnect layer; patterning a second dielectric layer on a second surface of said first substrate to provide access to said first through-substrate via; and forming a first bump making contact to said first through-substrate via.
Claim 2
Independent Claim
170 words
A method of forming through-substrate vias in a substrate, comprising the steps of: forming a first hollow region through a first substrate; depositing a first dielectric layer on a first surface of said first substrate and on inner surfaces of said first hollow region; depositing a first conductive layer through said first hollow region to form a first through-substrate via; removing said first conductive layer and said first dielectric layer from said first surface of said first substrate to leave said first through-substrate via isolated from said first substrate by said first dielectric layer; forming a first IC device layer on said first surface of said first substrate with circuit nodes electrically coupled to the through-substrate vias; forming a first interconnect layer on said first IC device layer; forming first inter-chip interconnects on said first interconnect layer; patterning a second dielectric layer on a second surface of said first substrate to provide access to said first through-substrate via; and forming a first bump making contact to said first through-substrate via.
Claim 3
Dependent Claim
182 words
The method of claim 1 further including the steps of: forming a second region through a second substrate; depositing a third dielectric layer on a first surface of said second substrate and on inner surfaces of said second region; depositing a second conductive layer through said second region; removing said second conductive layer and said third dielectric layer from said first surface of said second substrate to leave a second through-substrate via isolated from said second substrate by said third dielectric layer; forming a second IC device layer on said first surface of said second substrate with circuit nodes electrically coupled to the through-substrate vias; forming a second interconnect layer on said second IC device layer; forming second inter-chip interconnects on said second interconnect layer; patterning a fourth dielectric layer on a second surface of said second substrate to provide access to said second through-substrate via; forming a second bump making contact to said second through-substrate via; and joining said first and second bumps of said first and second substrates to provide electrical connectivity between said first and second IC device layers.
Claim 4
Independent Claim
159 words
A method of forming through-substrate vias in a substrate, comprising the steps of: forming a first IC device layer on a first surface of a first substrate; forming a first dielectric layer within said first IC device layer; forming a first pad within said first IC device layer isolated from said first substrate by said first dielectric layer; depositing a second dielectric layer on a second surface of said first substrate; etching a first region through said first substrate; depositing a third dielectric layer on said second dielectric layer and on inner surfaces of said first region for isolation; selectively removing portions of said first, second and third dielectric layers to expose said first pad; depositing a first conductive layer through said first region and contacting said first pad to form a first through-substrate via; and selectively removing said first conductive layer from said second surface of said first substrate to provide electrical isolation for said first through-substrate via.
Claim 5
Independent Claim
159 words
A method of forming through-substrate vias in a substrate, comprising the steps of: forming a first IC device layer on a first surface of a first substrate; forming a first dielectric layer within said first IC device layer; forming a first pad within said first IC device layer isolated from said first substrate by said first dielectric layer; depositing a second dielectric layer on a second surface of said first substrate; etching a first region through said first substrate; depositing a third dielectric layer on said second dielectric layer and on inner surfaces of said first region for isolation; selectively removing portions of said first, second and third dielectric layers to expose said first pad; depositing a first conductive layer through said first region and contacting said first pad to form a first through-substrate via; and selectively removing said first conductive layer from said second surface of said first substrate to provide electrical isolation for said first through-substrate via.
Claim 6
Dependent Claim
32 words
The method of claim 3 further including the steps of: depositing a fourth dielectric layer on said second dielectric layer; and forming a first bump making contact to said first through-substrate via.
Claim 7
Dependent Claim
201 words
The method of claim 4 further including the steps of: forming a second IC device layer on a first surface of a second substrate; forming a fifth dielectric layer within said second IC device layer; forming a second pad within said second IC device layer isolated from said second substrate by said fifth dielectric layer; depositing a sixth dielectric layer on a second surface of said second substrate; etching a second region through said second substrate; depositing a seventh dielectric layer on said sixth dielectric layer and on inner surfaces of said second region for isolation; selectively removing portions of said fifth, sixth and seventh dielectric layers to expose said second pad; depositing a second conductive layer through said second region and contacting said second pad to form a second through-substrate via; selectively removing said second conductive layer from said second surface of said second substrate to provide electrical isolation for said second through-substrate via; depositing an eighth dielectric layer on said sixth dielectric layer; forming a second bump making contact to said second through-substrate via; and joining said first and second bumps of said first and second substrates to provide electrical connectivity between said first and second IC device layers.
References Cited (Backward Citations)
US3648131A
Cited
US4754316A
Cited
US4761681A
Cited
US4807021A
Cited
US4954875A
Cited
JPH02239627A
Cited
US5037782A
Cited
US5139969A
Cited
US5059553A
Cited
US5229647A
Cited
JPH04356956A
Cited
US5366589A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-12 | 1998-12-12 | 1999-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-12 | 2002-12-12 | 2003-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-12 | 2006-12-12 | 2007-06-13 | $7700.00 | Window Closed / Lapsed |