Patent US6399892B1 successfully refreshed from Google Patents.
US6399892B1
Expired / Lapsed
US
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CTE compensated chip interposer
Assignee: International Business Machines Corp
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Filing: 2000-09-19
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Granted: 2002-06-04
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Expires: 2020-09-19
Abstract
Abstract A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.
Inventors
- 👤 Cynthia Susan Milkovich
- 👤 Mark Vincent Pierson
- 👤 Charles Gerard Woychik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:51
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4688; H05K1/00; H05K1/02; H05K1/0271; H10; H10W; H10W40/00; H10W40/20; H10W40/25; H10W40/255; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H05K1/03; H05K1/0313; H05K1/0353; H05K1/036; H05K1/11; H05K1/111; H05K1/112; H05K1/113; H05K1/14; H05K1/141; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0133; H05K2201/06; H05K2201/068; H05K2201/10; H05K2201/10227; H05K2201/10378; H05K2201/10613; H05K2201/10621; H05K2201/10674; H05K3/40; H05K3/42; H05K3/429; H05K3/4611; H05K3/4641; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W72/951; H10W72/952; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49128; Y10T29/4913; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
123 words
A CTE compensated semiconductor chip interposer comprising: a first layer of high elastic modulus dielectric material having a low CTE; a second layer of dielectric material with metallurgy formed thereon having a lower elastic modulus than the elastic modulus of said first layer of material and having a higher composite CTE than the CTE said of first layer of material; and a third layer of dielectric material with metallurgy formed thereon having a composite CTE between the CTEs of said first and second layers of dielectric material, said third layer of dielectric material laminated between said first layer of dielectric material and said second layer of dielectric material to form a multilayer interposer having formed therein an array of conductive vias extending therethrough.
Claim 2
Dependent Claim
123 words
A CTE compensated semiconductor chip interposer comprising: a first layer of high elastic modulus dielectric material having a low CTE; a second layer of dielectric material with metallurgy formed thereon having a lower elastic modulus than the elastic modulus of said first layer of material and having a higher composite CTE than the CTE said of first layer of material; and a third layer of dielectric material with metallurgy formed thereon having a composite CTE between the CTEs of said first and second layers of dielectric material, said third layer of dielectric material laminated between said first layer of dielectric material and said second layer of dielectric material to form a multilayer interposer having formed therein an array of conductive vias extending therethrough.
Claim 3
Dependent Claim
65 words
The interposer of claim 1 wherein the CTE of said first layer is between 3 and 8 PPM per degree C., the composite CTE of said second layer of dielectric material is between 15 and 20 PPM per degree C. and the composite CTE of said third layer of dielectric material is between the CTE ranges of said first and second layers of dielectric material.
Claim 4
Dependent Claim
52 words
The interposer of claim 2 wherein the elastic modulus of said first layer of dielectric material is between 10 Mpsi and 55 Mpsi, the elastic modulus of said second layer of dielectric material is between 1 and 3 Mpsi and the elastic modulus of said third layer is less than 1 Mpsi.
Claim 5
Dependent Claim
46 words
The interposer of claim 1 wherein said first layer of dielectric material is selected from among ceramic, glass and semiconductor materials, said second layer of dielectric material is selected from among circuit board materials and said third layer of dielectric material is a Teflon/glass particle material.
Claim 6
Dependent Claim
54 words
The interposer of claim 4 wherein said second layer of dielectric material with metallurgy formed thereon comprises a laminate of two thin layers of circuit board material separated on their inner surfaces by a layer of copper circuit lines and with each layer having a layer of copper circuit lines on their outer surface.
Claim 7
Dependent Claim
32 words
The interposer of claim 5 wherein said third layer of dielectric material with metallurgy formed thereon comprises a laminate of two thin layers of Teflon/glass particle material separated by a metal layer.
Claim 8
Dependent Claim
13 words
The interposer of claim 6 wherein said metal layer is copper-invar-copper reference plane.
Claim 9
Dependent Claim
204 words
An interposer for connecting a chip to a laminate chip carrier through a pattern of conductive vias comprising: a first layer of dielectric material having a CTE closer to the CTE of said chip than to said laminate chip carrier and made of a relatively stiff high elastic modulus material so as to resist bending during thermal cycling when laminated with a layer of material having a different CTE; a second layer of dielectric material with metallurgy formed thereon having a composite CTE different than the CTE of said first layer which composite CTE is closer to the CTE of said laminate chip carrier than to the CTE of said chip and which is made of a flexible low elastic modulus material so as to give during thermal cycling when laminated with said first layer of dielectric material; and a third layer of dielectric material with metallurgy formed thereon laminated between said first and second layers of dielectric material and having a composite CTE between the CTE of said first and second layers of dielectric material and made of a flexible low elastic modulus material so as to absorb the thermal expansion differences between said first and second layers of material during thermal cycling.
Claim 10
Dependent Claim
204 words
An interposer for connecting a chip to a laminate chip carrier through a pattern of conductive vias comprising: a first layer of dielectric material having a CTE closer to the CTE of said chip than to said laminate chip carrier and made of a relatively stiff high elastic modulus material so as to resist bending during thermal cycling when laminated with a layer of material having a different CTE; a second layer of dielectric material with metallurgy formed thereon having a composite CTE different than the CTE of said first layer which composite CTE is closer to the CTE of said laminate chip carrier than to the CTE of said chip and which is made of a flexible low elastic modulus material so as to give during thermal cycling when laminated with said first layer of dielectric material; and a third layer of dielectric material with metallurgy formed thereon laminated between said first and second layers of dielectric material and having a composite CTE between the CTE of said first and second layers of dielectric material and made of a flexible low elastic modulus material so as to absorb the thermal expansion differences between said first and second layers of material during thermal cycling.
Claim 11
Dependent Claim
59 words
The interposer as set forth in claim 8 wherein said second layer of dielectric material with metallurgy formed thereon comprises a laminate of two thin layers of circuit board material separated by a pattern of conductive circuit lines on the inner surfaces thereof and with each layer having a pattern of conductive circuit lines on the outer surface thereof.
Claim 12
Dependent Claim
36 words
The interposer as set forth in claim 9 wherein said third layer of dielectric material with metallurgy formed thereon comprises a laminate of two thin layers of dielectric material separated by a conductive layer of material.
Claim 13
Dependent Claim
31 words
The interposer as set forth in claim 10 wherein said two thin layers of dielectric material of said third layer are made of Teflon/glass particles and said conductive layer is copper-invar-copper.
Claim 14
Dependent Claim
35 words
The interposer as set forth in claim 11 wherein said first layer of material has a CTE between 3 and 8 PPM per degree C. and an elastic modulus of between 10 and 55 Mpsi.
Claim 15
Dependent Claim
23 words
The interposer as set forth in claim 12 wherein said first layer of material is selected from among ceramic, glass and semiconductor material.
Claim 16
Dependent Claim
14 words
The interposer as set forth in claim 13 wherein said semiconductor material is silicon.
Claim 17
Dependent Claim
170 words
An electronic package, comprising: a semiconductor chip die having an array of conductive pads on one surface thereof; a chip carrier having an array of conductive pads corresponding to the array of conductive pads on said semiconductor chip die; and a multilayer interposer positioned between said chip die and chip carrier having an array of conductive vias respectively connecting the said conductive pads of said semiconductor chip die to the said conductive pads of said chip carrier, said multilayer interposer including; a first layer of high elastic modulus dielectric material having a CTE closely matching the CTE of said semiconductor chip die; a second layer of material having a lower elastic modulus than the elastic modulus of said first layer of material and having a CTE closely matching the CTE of said chip carrier, and a third layer of material having a lower elastic modulus than the elastic modulus of said first layer of material and having a CTE between the CTEs of said first and second layers of material.
Claim 18
Dependent Claim
170 words
An electronic package, comprising: a semiconductor chip die having an array of conductive pads on one surface thereof; a chip carrier having an array of conductive pads corresponding to the array of conductive pads on said semiconductor chip die; and a multilayer interposer positioned between said chip die and chip carrier having an array of conductive vias respectively connecting the said conductive pads of said semiconductor chip die to the said conductive pads of said chip carrier, said multilayer interposer including; a first layer of high elastic modulus dielectric material having a CTE closely matching the CTE of said semiconductor chip die; a second layer of material having a lower elastic modulus than the elastic modulus of said first layer of material and having a CTE closely matching the CTE of said chip carrier, and a third layer of material having a lower elastic modulus than the elastic modulus of said first layer of material and having a CTE between the CTEs of said first and second layers of material.
Claim 19
Dependent Claim
54 words
The electronic package of claim 15 wherein the elastic modulus of said first layer of dielectric material is between 10 Mpsi and 55 Mpsi, the elastic modulus of said second layer of material is between 1 and 3 Mpsi and the elastic modulus of aid third layer of material is less than 1 Mpsi.
Claim 20
Dependent Claim
46 words
The electronic package of claim 16 wherein said first layer of dielectric material is selected from among ceramic, glass and semiconductor materials, said second layer of material includes material selected from among circuit board materials and said third layer of material includes a Teflon/glass particle material.
Claim 21
Dependent Claim
51 words
The electronic package of claim 17 wherein said second layer of material comprises a laminate of two thin layers of circuit board material separated on their inner surfaces by a layer of conductive circuit lines and with each layer having a layer of conductive circuit lines on their outer surface thereof.
Claim 22
Dependent Claim
28 words
The electronic package of claim 18 wherein said third layer of material comprises a laminate of two thin layers of Teflon/glass particle material separated by a conductive layer.
Claim 23
Dependent Claim
31 words
The electronic package of claim 19 wherein said layers of conductive lines of said second layer of material and said conductive layer of said third layer of material are copper based.
References Cited (Backward Citations)
US4025997A
Cited
US4349862A
Cited
US4609586A
Cited
US4825284A
Cited
US4821142A
Cited
US5189507A
Cited
US4876120A
Cited
US4937707A
Cited
US4943468A
Cited
US5065227A
Cited
US5682061A
Cited
US5248853A
Cited
US5483421A
Cited
US5313366A
Cited
US5386341A
Cited
US5571608A
Cited
US5574630A
Cited
US5796591A
Cited
US5841194A
Cited
US5943212A
Cited
US6090468A
Cited
US5888631A
Cited
US5900312A
Cited
US6248959B1
Cited
US5798563A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-03 | 2005-12-03 | 2006-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-03 | 2009-12-03 | 2010-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-03 | 2013-12-03 | 2014-06-04 | $7700.00 | Window Closed / Lapsed |