US6388294B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit using damascene gate structure
Assignee: International Business Machines Corp
•
Filing: 2000-11-22
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Granted: 2002-05-14
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Expires: 2020-11-22
Abstract
Abstract An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.
Inventors
- 👤 Carl Radens
- 👤 Mary E. Weybright
- 👤 Gary Bronner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:22
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0217; H10D64/00; H10D64/01; H10D64/017; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/013; H10D84/0133; H10D84/0135; H10D84/014; H10D84/02; H10D84/03; H10D84/038; H10D30/0212
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
62 words
An integrated circuit device, comprising: a semiconductor substrate; first gate electrodes formed on the semiconductor substrate; and at least one second gate electrode formed at a selected region of the semiconductor substrate by stripping one of the first gate electrodes to the semiconductor substrate and forming the second gate electrode by a damascene process in place of the removed first gate electrode.
Claim 2
Dependent Claim
62 words
An integrated circuit device, comprising: a semiconductor substrate; first gate electrodes formed on the semiconductor substrate; and at least one second gate electrode formed at a selected region of the semiconductor substrate by stripping one of the first gate electrodes to the semiconductor substrate and forming the second gate electrode by a damascene process in place of the removed first gate electrode.
Claim 3
Dependent Claim
117 words
The device as in claim 1 , further comprising: a well region formed within the semiconductor substrate; source/drain regions formed within the semiconductor substrate, the source/drain regions being adjacent to and self-aligned with the first gate electrodes and second gate electrode; first sidewall spacers formed on the first gate electrodes; a first interlevel dielectric layer deposited over the first gate electrodes and elsewhere on the semiconductor substrate, the first interlevel layer being planarized to upper surfaces of the first gate electrodes; a second interlevel dielectric layer deposited over the first and second gate electrodes and the first interlevel dielectric layer; and a plurality of contacts to form electrical interconnections over the well region, including the source/drain regions.
Claim 4
Dependent Claim
28 words
The device as in claim 1 , wherein the semiconductor substrate includes first and second self-aligned channels formed therein generally below the first and second gate electrodes, respectively.
Claim 5
Dependent Claim
28 words
The device as in claim 3 , wherein the plurality of contacts comprises a contact to the second gate conductor, a diffusion contact, and a self-aligned diffusion contact.
Claim 6
Dependent Claim
24 words
The device as in claim 3 , wherein the self-aligned diffusion contact partially overlaps the gate cap dielectric layer of the first gate electrode.
Claim 7
Dependent Claim
36 words
The device as in claim 1 , further comprising: first sidewall spacers formed adjacent to and self-aligned with the first gate electrodes; and second sidewall spacers formed adjacent to and self-aligned with the second gate electrodes.
Claim 8
Dependent Claim
46 words
The device as in claim 1 , wherein the first gate electrode comprises: a first gate oxide layer formed on the semiconductor substrate; a first gate conductor deposited on the first gate oxide layer; and a gate cap dielectric layer deposited on the first gate conductor.
Claim 9
Dependent Claim
42 words
The device as in claim 1 , wherein the second gate electrode comprises: a second gate oxide formed on the semiconductor substrate; a second gate conductor deposited on the second gate oxide; and a salicide layer formed on the second gate conductor.
Claim 10
Dependent Claim
18 words
The device as in claim 1 , wherein the second gate electrode is formed by a damascene process.
Claim 11
Dependent Claim
29 words
The device as in claim 1 , wherein the second gate electrode is formed in between sidewall spacers formed adjacent to and self-aligned with the removed first gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-05-13 | 2005-11-12 | 2006-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-13 | 2009-11-12 | 2010-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-13 | 2013-11-12 | 2014-05-14 | $7700.00 | Window Closed / Lapsed |