Process for simultaneous formation of trench contact and vertical transistor gate and structure

Abstract

Abstract The described embodiments of the present invention provide structures and methods for fabricating the structures which provide compact contact from the surface of an integrated circuit to a buried layer formed in conjunction with a vertical gate extending from the buried layer to a doped layer at a surface of the integrated circuit. In one embodiment, trenches are simultaneously formed for providing the vertical gate and the contact to the buried layer. A thermal oxide layer is formed on the surface of the integrated circuit to provide an insulating layer on the surfaces of both the contact trench and the gate trench. A first layer of in situ doped polycrystalline silicon is deposited on the surface of the integrated circuit. The thickness of this polycrystalline silicon layer is chosen so as to not fill the gate and contact trenches. A masking layer is then provided to protect the gate trench and expose the contact trench. An anisotropic etching process is then performed which removes the bottom portion of the polycrystalline silicon layer and the thus exposed portion of the gate oxide at the bottom of the contact trench. The masking layer is removed and the balance of the trenches is filled with a second in situ doped polycrystalline silicon layer which fills the gate trench to provide a high conductivity vertical gate and fills the contact trench. At the bottom of the contact trench, the second polycrystalline silicon layer is in contact with the substrate, some of the dopant atoms in the first and second polycrystalline silicon layers will diffue into the buried layer.

Inventors

• 👤 Robert H. Eklund
• 👤 Roger Haken

Bibliographic Details