Semiconductor device with deep grip accessible via the surface and process for manufacturing same

Claim 2

A process for manufacturing a semiconductor device on a semiconductor substrate, the device including different layers of distinct conductivity type and/or doping levels, said device including an array of highly doped regions of a first conductivity type buried in a region of a second conductivity type opposite to the first type, said array being conductively connected to a metallization layer formed on a major surface of the substrate, said process comprising the following steps: coating said major surface of the substrate with a layer of a first protecting substance, selectively etching said first substance according to a predetermined pattern corresponding to said array to be formed, anisotropically etching the substrate where it is not covered by said first substance, to form vertical grooves having vertical lateral walls and a bottom wall, said grooves extending to a first depth from said major surface of the substrate, forming on the vertical walls and bottom wall of the grooves a coating of a second, electrically insulating, protecting substance, removing said second substance from the bottom wall of the grooves through an anisotropic etching process while keeping said second substance on the vertical walls, and keeping said first substance outside said grooves, deepening said grooves where they are not coated with said second protecting substance, by an anisotropic etching process, thereby vertically increasing the depth of the grooves to a depth greater than said first depth, and filling the grooves with a conductive material to make electrical contact at the bottom of the grooves between said conductive material and said semiconductor substrate, said conductive material being insulated from said substrate by said second protecting layer along the vertical walls of the grooves from the surface of the substrate down to said first depth.

Claim 3

A process according to claim 1, wherein said first substance is silicon nitride, said second substance is silicon oxide and said conductive material is polycrystalline silicon.

Claim 4

A process for manufacturing a semiconductor device on a semiconductor substrate including layers of distinct conductivity type and/or doping levels, said device including an array of grooves filled with conductive material contacting the semiconductor substrate at the bottom of the grooves, said process comprising the following steps: coating a major surface of the substrate with a layer of silicon nitride, selectively etching said layer of silicon nitride according to a predetermined pattern corresponding to said array to be formed, anisotropically etching the substrate where it is not covered by silicon nitride, to form vertical grooves having vertical lateral walls and a bottom wall, forming on the vertical walls of the grooves a coating of an insulating substance, removing said insulating substance from the bottom wall of the grooves through an anisotropic etching process while keeping said insulating substance on the vertical walls and while keeping said silicon nitride on the substance outside said grooves, filling the grooves with an oxidizable conductive material to make electrical contact between said conductive material and the substrate at the bottom of the grooves, said conductive material being insulated from said substrate by said insulating substance on the vertical walls of the grooves, removing any oxidizable conductive material outside said grooves by plasma etching, oxidizing an upper portion of said conductive material, oxidation of the substrate outside the grooves being prevented by said layer of silicon nitride, removing the silicon nitride layer, selectively etching the oxidized conductive material at selected places, and depositing and etching a metallization layer of which some portions contact the major surface of the substrate between the grooves and other portions contact the oxidizable conductive material at said selected places.

Claim 5

A process for manufacturing a semiconductor device on a semiconductor substrate including layers of distinct conductivity type and/or doping levels, said device including an array of grooves filled with conductive material contacting the semiconductor substrate at the bottom of the grooves, said process comprising the following steps: coating a major surface of the substrate with a layer of silicon nitride, selectively etching said layer of silicon nitride according to a predetermined pattern corresponding to said array to be formed, anisotropically etching the substrate where it is not covered by silicon nitride, to form vertical grooves having vertical lateral walls and a bottom wall, forming on the vertical walls of the grooves a coating of an insulating substance, removing said insulating substance from the bottom wall of the grooves through an anisotropic etching process while keeping said insulating substance on the vertical walls and while keeping said silicon nitride on the substance outside said grooves, filling the grooves with an oxidizable conductive material to make electrical contact between said conductive material and the substrate at the bottom of the grooves, said conductive material being insulated from said substrate by said insulating substance on the vertical walls of the grooves, removing any oxidizable conductive material outside said grooves by plasma etching, oxidizing an upper portion of said conductive material, oxidation of the substrate outside the grooves being prevented by said layer of silicon nitride, removing the silicon nitride layer, selectively etching the oxidized conductive material at selected places, and depositing and etching a metallization layer of which some portions contact the major surface of the substrate between the grooves and other portions contact the oxidizable conductive material at said selected places.