US4910567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dram cell and method for fabricating
Assignee: Texas Instruments Inc
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Filing: 1986-02-26
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Granted: 1990-03-20
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Expires: 2006-02-26
Abstract
Abstract The described embodiment of the present invention provides a memory cell which is fabricated using a self-isolating structure and provides misalignment tolerance in the design of the cell thereby eliminating the need for additional area to be reserved for isolation structures and misalignment tolerances.
Inventors
- 👤 Satwinder Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:49
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
189 words
A memory array comprising: a plurality of memory cells formed in a substrate having trenches formed therein which define a mesa in said substrate for each of said memory cells; a region of a conductivity opposite the conductivity of said substrate formed in the sidewalls and on the surface of said mesa; dielectric material formed in said trenches; an epitaxial layer formed into a plurality of substantially parallel strips, each parallel strip contacting the top surface of a plurality of said mesas, said epitaxial layer containing a bottom region of the same conductivity type as said substrate contacting said mesas and a top region of opposite conductivity type of said substrate, said top region of each of said strips serving as a bit line; an insulating layer formed on the surface of said epitaxial layer and on any of the top surfaces of said mesas left exposed by the formation of said epitaxial layer; and a plurality of conductive strips formed on the surface of said insulating layer, said strips running substantially perpendicular to said parallel strips of said epitaxial layer each of said strips serving as word line.
Claim 2
Dependent Claim
189 words
A memory array comprising: a plurality of memory cells formed in a substrate having trenches formed therein which define a mesa in said substrate for each of said memory cells; a region of a conductivity opposite the conductivity of said substrate formed in the sidewalls and on the surface of said mesa; dielectric material formed in said trenches; an epitaxial layer formed into a plurality of substantially parallel strips, each parallel strip contacting the top surface of a plurality of said mesas, said epitaxial layer containing a bottom region of the same conductivity type as said substrate contacting said mesas and a top region of opposite conductivity type of said substrate, said top region of each of said strips serving as a bit line; an insulating layer formed on the surface of said epitaxial layer and on any of the top surfaces of said mesas left exposed by the formation of said epitaxial layer; and a plurality of conductive strips formed on the surface of said insulating layer, said strips running substantially perpendicular to said parallel strips of said epitaxial layer each of said strips serving as word line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |