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JPS5651854A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: CHIYOU LSI GIJUTSU KENKYU KUMIAI
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Filing: 1979-10-04
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Granted: —
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Expires: 1999-10-04
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Abstract

Abstract PURPOSE:To eliminate the masking for an accumulation layer and a drain so as to enable the memory device to be highly integrated, by providing the charge accumulation layer in deep section of a substrate under a gate electrode and a drain. CONSTITUTION:By separating a P type Si substrate 11 with a field oxide film 12, a poly Si gate electrode 14 (word line W) is prepared on a gate oxide film 13. An N<+> drain 15 (bit line) is prepared on the surface of the exposed substrate 11, and P<+> layer 16 is provided under the layer 15. Further, an N<+> layer 17 is prepared in deep section of the substrate under the gate electrode 14 and the drain 15, a P<+> layer 18 is provided under the layer 17, and charge is accumulated on a channel between the layers 17 and 18. It is possible, by using this constitution, to eliminate necessity of allowance for masking for formation of the layers 17 and 18 and the drain 15, and therefore, it can be made in smaller size, and the integration can be remarkably improved. This drain-equipped MOS capacity is able to read and print information with simplicity.

Inventors

  • 👤 Kanji Hirabayashi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 02:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/33

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