US5767005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a flash EEPROM
Assignee: Round Rock Research LLC
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Filing: 1995-09-25
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Granted: 1998-06-16
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Expires: 2015-09-25
Abstract
Abstract A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
Inventors
- 👤 Trung Tri Doan
- 👤 Tyler A. Lowrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
96 words
A method for forming a semiconductor device comprising: providing a substrate with an active area; forming a first layer on the substrate, said first layer including a first recess enclosing the active area; forming a mask in the first recess configured to protect the active area; forming a field oxide on the first layer using the mask, said field oxide including a second recess aligned with the first recess; removing the mask; forming a conductive layer on the field oxide and the second recess; and planarizing the conductive layer to a surface of the field oxide.
Claim 2
Independent Claim
96 words
A method for forming a semiconductor device comprising: providing a substrate with an active area; forming a first layer on the substrate, said first layer including a first recess enclosing the active area; forming a mask in the first recess configured to protect the active area; forming a field oxide on the first layer using the mask, said field oxide including a second recess aligned with the first recess; removing the mask; forming a conductive layer on the field oxide and the second recess; and planarizing the conductive layer to a surface of the field oxide.
Claim 3
Dependent Claim
17 words
The method as recited in claim 1 wherein planarizing the conductive layer comprises chemical mechanical planarization (CMP).
Claim 4
Dependent Claim
28 words
The method as recited in claim 1 further comprising forming an insulating layer on the conductive layer and then forming a second conductive layer on the insulation layer.
Claim 5
Dependent Claim
17 words
The method as recited in claim 1 wherein forming the mask comprises a chemical mechanical planarization step.
Claim 6
Dependent Claim
19 words
The method as recited in claim 1 wherein forming the field oxide comprises a local oxidation of silicon process.
Claim 7
Dependent Claim
13 words
The method as recited in claim 1 wherein the conductive layer comprises polysilicon.
Claim 8
Dependent Claim
19 words
The method as recited in claim 1 wherein the semiconductor device comprises an electrically erasable programmable read only memory.
Claim 9
Independent Claim
110 words
A method for forming a semiconductor device comprising: providing a silicon substrate with a gate area; forming a first layer on the substrate, said first layer including a first recess enclosing the gate area; forming a mask within the first recess; forming a field oxide on the first layer, said field oxide including a second recess aligned with the first recess, said second recess enclosing the gate area; removing the mask; forming a conductive layer on the field oxide, said conductive layer extending into the second recess; and planarizing the conductive layer to a surface of the field oxide to form a floating gate self aligned with the gate area.
Claim 10
Independent Claim
110 words
A method for forming a semiconductor device comprising: providing a silicon substrate with a gate area; forming a first layer on the substrate, said first layer including a first recess enclosing the gate area; forming a mask within the first recess; forming a field oxide on the first layer, said field oxide including a second recess aligned with the first recess, said second recess enclosing the gate area; removing the mask; forming a conductive layer on the field oxide, said conductive layer extending into the second recess; and planarizing the conductive layer to a surface of the field oxide to form a floating gate self aligned with the gate area.
Claim 11
Dependent Claim
17 words
The method as claimed in claim 8 wherein planarizing the conductive layer comprises chemical mechanical planarization (CMP).
Claim 12
Dependent Claim
26 words
The method as claimed in claim 8 further comprising: forming an insulating layer on the conductive layer; and forming a control gate on the insulating layer.
Claim 13
Dependent Claim
28 words
The method as claimed in claim 10 further comprising forming the semiconductor device in a memory array and removing the insulating layer from peripheral devices of the array.
Claim 14
Dependent Claim
14 words
The method as claimed in claim 8 wherein the conductive layer comprises doped polysilicon.
Claim 15
Dependent Claim
14 words
The method as claimed in claim 8 wherein the conductive layer comprises a metal.
Claim 16
Dependent Claim
18 words
The method as claimed in claim 8 wherein the semiconductor device comprises an electrically programmable read only memory.
Claim 17
Independent Claim
97 words
A method for forming a semiconductor device comprising: providing a silicon substrate with a gate area; forming a first layer on the substrate, said first layer including a first recess enclosing the gate area; forming a mask on the gate area; forming a field oxide on the first layer with the gate area protected by the mask, said field oxide including a second recess enclosing the gate area; forming a conductive layer on the gate area; and planarizing the conductive layer to a surface of the field oxide to form a floating gate on the gate area.
Claim 18
Independent Claim
97 words
A method for forming a semiconductor device comprising: providing a silicon substrate with a gate area; forming a first layer on the substrate, said first layer including a first recess enclosing the gate area; forming a mask on the gate area; forming a field oxide on the first layer with the gate area protected by the mask, said field oxide including a second recess enclosing the gate area; forming a conductive layer on the gate area; and planarizing the conductive layer to a surface of the field oxide to form a floating gate on the gate area.
Claim 19
Dependent Claim
16 words
The method as claimed in claim 15 wherein the planarizing step comprises chemical mechanical planarization (CMP).
Claim 20
Dependent Claim
34 words
The method as claimed in claim 15 wherein forming the mask comprises depositing a mask layer in the first recess and chemically mechanically planarizing the mask layer to a surface of the first layer.
Claim 21
Dependent Claim
19 words
The method as claimed in claim 15 wherein the semiconductor device comprises an electrically erasable programmable read only memory.
Claim 22
Independent Claim
145 words
A method for forming a semiconductor device comprising: providing a silicon substrate; forming an isolation oxide on the substrate, said isolation oxide including a first recess; depositing a mask layer on the isolation oxide and into the first recess; chemically mechanically planarizing (CMP) the mask layer to a surface of the isolation oxide to form a mask covering the substrate in the first recess; growing a field oxide on the substrate using the mask, said field oxide including a second recess aligned with said first recess; removing the mask; forming a conductive layer on the field oxide and into the second recess; planarizing the conductive layer to a surface of the field oxide to remove the conductive layer except within the second recess to form a floating gate; forming an insulating layer on the conductive layer; and forming a control gate on the insulating layer.
Claim 23
Independent Claim
145 words
A method for forming a semiconductor device comprising: providing a silicon substrate; forming an isolation oxide on the substrate, said isolation oxide including a first recess; depositing a mask layer on the isolation oxide and into the first recess; chemically mechanically planarizing (CMP) the mask layer to a surface of the isolation oxide to form a mask covering the substrate in the first recess; growing a field oxide on the substrate using the mask, said field oxide including a second recess aligned with said first recess; removing the mask; forming a conductive layer on the field oxide and into the second recess; planarizing the conductive layer to a surface of the field oxide to remove the conductive layer except within the second recess to form a floating gate; forming an insulating layer on the conductive layer; and forming a control gate on the insulating layer.
Claim 24
Dependent Claim
14 words
The method as claimed in claim 19 wherein the mask layer comprises silicon nitride.
Claim 25
Dependent Claim
17 words
The method as claimed in claim 19 wherein planarizing the conductive layer comprises chemical mechanical planarization (CMP).
Claim 26
Dependent Claim
19 words
The method as claimed in claim 19 wherein the semiconductor device comprises an electrically erasable programmable read only memory.
Claim 27
Independent Claim
149 words
A method for forming an electrically erasable programmable read only memory comprising: providing a silicon substrate with a gate area; forming a first layer on the substrate, said first layer including a first recess enclosing the gate area; depositing a second layer on the first layer and within the first recess; planarizing the second layer to a surface of the first layer to form a mask within the recess; growing a field oxide on the second layer with the gate area protected by the mask, said field oxide including a second recess aligned with the first recess, said second recess enclosing and electrically isolating the gate area; removing the mask; forming a conductive layer on the field oxide, said conductive layer extending into the second recess; and planarizing the conductive layer to a surface of the field oxide to form a floating gate self aligned with the active area.
Claim 28
Independent Claim
149 words
A method for forming an electrically erasable programmable read only memory comprising: providing a silicon substrate with a gate area; forming a first layer on the substrate, said first layer including a first recess enclosing the gate area; depositing a second layer on the first layer and within the first recess; planarizing the second layer to a surface of the first layer to form a mask within the recess; growing a field oxide on the second layer with the gate area protected by the mask, said field oxide including a second recess aligned with the first recess, said second recess enclosing and electrically isolating the gate area; removing the mask; forming a conductive layer on the field oxide, said conductive layer extending into the second recess; and planarizing the conductive layer to a surface of the field oxide to form a floating gate self aligned with the active area.
Claim 29
Dependent Claim
16 words
The method as claimed in claim 23 wherein planarizing the second layer comprises chemical mechanical planarization.
References Cited (Backward Citations)
US4818725A
Cited
US4833094A
Cited
US4997781A
Cited
US5292673A
Cited
US5032881A
Cited
US5290721A
Cited
US5196353A
Cited
US5315142A
Cited
US5270234A
Cited
US5521108A
Cited
US5407534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-15 | 2001-12-15 | 2002-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-15 | 2005-12-15 | 2006-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-15 | 2009-12-15 | 2010-06-16 | $7700.00 | Window Closed / Lapsed |