US6153459A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating dual gate structure of embedded DRAM
Assignee: United Microelectronics Corp
•
Filing: 1998-11-16
•
Granted: 2000-11-28
•
Expires: 2018-11-16
Abstract
Abstract A method of fabricating a dual gate of embedded DRAM forms a conductive layer on a substrate having a memory cell region and a logic circuitry. A gate structure is then formed on the substrate of the memory cell region and the conductive layer of the logic circuitry is removed by patterning the conductive layer. A polysilicon layer is then deposited and a dual gate structure is formed by patterning the polysilicon layer, and simultaneously, a polysilicon spacer is formed on the sidewall of the gate structure in the logic circuitry. The polysilicon spacer is then removed. An insulated spacer is formed on the sidewall of the gate structure and the dual gate structure, and a silicide layer is formed on the dual gate structure and the exposed substrate of the logic circuitry.
Inventors
- 👤 Shih-Wei Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:32
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/09
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
124 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a conductive layer on the substrate; forming a gate structure in the memory cell region and exposing the substrate in the logic circuitry by patterning the conductive layer; forming a dual gate structure in the logic circuitry, such that a polysilicon spacer is formed on the sidewall of the gate structure in the memory cell region; removing the polysilicon spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 2
Independent Claim
124 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a conductive layer on the substrate; forming a gate structure in the memory cell region and exposing the substrate in the logic circuitry by patterning the conductive layer; forming a dual gate structure in the logic circuitry, such that a polysilicon spacer is formed on the sidewall of the gate structure in the memory cell region; removing the polysilicon spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 3
Dependent Claim
32 words
The method according to claim 1, wherein before the step of forming a silicide layer comprises forming a source/drain region on the substrate beside the gate structure and the dual gate structure.
Claim 4
Dependent Claim
17 words
The method according to claim 1, wherein the method of removing the polysilicon spacer comprises wet etching.
Claim 5
Dependent Claim
13 words
The method according to claim 1, wherein the insulated spacer comprises nitride spacer.
Claim 6
Dependent Claim
47 words
The method according to claim 1, wherein forming a silicide further comprises forming a titanium layer on the substrate; performing a thermal process to form the silicide layer on the exposed substrate and the dual gate structure in the logic circuitry; and removing the unreacted titanium layer.
Claim 7
Independent Claim
162 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a first gate oxide layer, a first polysilicon layer, a tungsten silicide layer and a cap layer on the substrate; forming a gate structure in the memory cell region and exposing the first gate oxide layer in the logic circuitry by patterning the cap layer, the tungsten silicide layer, the first polysilicon layer and the gate oxide layer; forming a second polysilicon layer; forming a dual gate structure in the logic circuitry and a polysilicon spacer on the sidewall of the gate structure in the memory cell region by patterning the second polysilicon layer; removing the polysilicon spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 8
Independent Claim
162 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a first gate oxide layer, a first polysilicon layer, a tungsten silicide layer and a cap layer on the substrate; forming a gate structure in the memory cell region and exposing the first gate oxide layer in the logic circuitry by patterning the cap layer, the tungsten silicide layer, the first polysilicon layer and the gate oxide layer; forming a second polysilicon layer; forming a dual gate structure in the logic circuitry and a polysilicon spacer on the sidewall of the gate structure in the memory cell region by patterning the second polysilicon layer; removing the polysilicon spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 9
Dependent Claim
50 words
The method according to claim 6, wherein after the step of forming a gate structure and before the step of forming a second polysilicon layer further comprises removing the first gate oxide layer of the logic circuitry; and forming a second gate oxide layer on the substrate of the circuitry.
Claim 10
Dependent Claim
16 words
The method according to claim 7, wherein removing the first gate oxide layer comprises wet etching.
Claim 11
Dependent Claim
17 words
The method according to claim 6, wherein the step of removing the polysilicon spacer comprises wet etching.
Claim 12
Dependent Claim
57 words
The method according to claim 6, wherein forming an insulated spacer on the sidewalls of the gate structure and the dual gate structure further comprises forming an insulated layer over the substrate; and patterning the insulated layer to form the insulated spacer on the sidewalls of the gate structure and the dual gate structure by anisotropic etching.
Claim 13
Dependent Claim
14 words
The method according to claim 9, wherein the insulated layer comprises silicon nitride layer.
Claim 14
Independent Claim
75 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a conductive layer on the substrate; forming a gate structure in the memory cell region and exposing the substrate of the logic circuitry by patterning the conductive layer; forming a polysilicon layer over the substrate; and forming a dual gate structure in the logic circuitry by patterning the polysilicon layer.
Claim 15
Independent Claim
75 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a conductive layer on the substrate; forming a gate structure in the memory cell region and exposing the substrate of the logic circuitry by patterning the conductive layer; forming a polysilicon layer over the substrate; and forming a dual gate structure in the logic circuitry by patterning the polysilicon layer.
Claim 16
Dependent Claim
35 words
The method according to claim 12, wherein forming a dual gate structure in the logic circuitry by patterning the polysilicon layer further comprises a polysilicon spacer formed on the sidewall of the gate structure 316.
Claim 17
Independent Claim
133 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a conductive layer on the substrate; forming a cap layer on the conductive layer; forming a gate structure in the memory cell region and exposing the substrate in the logic circuitry by patterning the conductive layer; forming a dual gate structure in the logic circuitry, such that a polysilicon spacer is formed on the sidewall of the gate structure in the memory cell region; removing the polysilicon layer spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 18
Independent Claim
133 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a conductive layer on the substrate; forming a cap layer on the conductive layer; forming a gate structure in the memory cell region and exposing the substrate in the logic circuitry by patterning the conductive layer; forming a dual gate structure in the logic circuitry, such that a polysilicon spacer is formed on the sidewall of the gate structure in the memory cell region; removing the polysilicon layer spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 19
Independent Claim
165 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a first gate oxide layer, a first polysilicon layer, a tungsten silicide layer, and a cap layer comprising silicon nitride, on the substrate; forming a gate structure in the memory cell region and exposing the first gate oxide layer in the logic circuitry by patterning the cap layer, the tungsten silicide layer, the first polysilicon layer and the gate oxide layer; forming a second polysilicon layer; forming a dual gate structure in the logic circuitry and a polysilicon spacer on the sidewall of the gate structure in the memory cell region by patterning the second polysilicon layer; removing the polysilicon spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 20
Independent Claim
165 words
A method of fabricating a dual gate structure of embedded DRAM, comprising: providing a substrate having a memory cell region and a logic circuitry; forming a first gate oxide layer, a first polysilicon layer, a tungsten silicide layer, and a cap layer comprising silicon nitride, on the substrate; forming a gate structure in the memory cell region and exposing the first gate oxide layer in the logic circuitry by patterning the cap layer, the tungsten silicide layer, the first polysilicon layer and the gate oxide layer; forming a second polysilicon layer; forming a dual gate structure in the logic circuitry and a polysilicon spacer on the sidewall of the gate structure in the memory cell region by patterning the second polysilicon layer; removing the polysilicon spacer in the memory cell region; forming an insulated spacer on the sidewall of the gate structure and the dual gate structure; and forming a silicide layer on the exposed substrate and the dual gate structure in the logic circuitry.
Claim 21
Dependent Claim
12 words
The method according to claim 15, wherein the silicide layer comprises salicide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |