Dual gate oxide process with increased reliability

Claim 1

A method comprising the following steps: (a) forming gate oxide within regions on a substrate; (b) forming polysilicon over a first region, the polysilicon extending over field oxide surrounding the first region; (c) thinning gate oxide within a second region, the polysilicon over the first region preventing gate oxide within the first region from being thinned; (d) forming a first transistor gate within the second region, including the following substeps: (d.1) depositing a layer of polysilicon, (d.2) depositing a layer of metal-silicide, (d.3) depositing a dielectric layer, and (d.4) etching the dielectric layer, the layer of metal-silicide and the layer of polysilicon to form the first transistor gate; and, (e) after forming the first transistor gate within the second region, etching the polysilicon which is over the first region to form a second transistor gate.

Claim 2

A method comprising the following steps: (a) forming gate oxide within regions on a substrate; (b) forming polysilicon over a first region, the polysilicon extending over field oxide surrounding the first region; (c) thinning gate oxide within a second region, the polysilicon over the first region preventing gate oxide within the first region from being thinned; (d) forming a first transistor gate within the second region, including the following substeps: (d.1) depositing a layer of polysilicon, (d.2) depositing a layer of metal-silicide, (d.3) depositing a dielectric layer, and (d.4) etching the dielectric layer, the layer of metal-silicide and the layer of polysilicon to form the first transistor gate; and, (e) after forming the first transistor gate within the second region, etching the polysilicon which is over the first region to form a second transistor gate.

Claim 6

A method comprising the following steps: (a) forming gate oxide within regions on a substrate; (b) forming gate material over a first region, the gate material extending over field oxide surrounding the first region; (c) stripping gate oxide within a second region, the gate material over the first region preventing gate oxide within the first region from being stripped; (d) forming a new layer of gate oxide within the second region; (e) forming a first transistor gate within the second region, including the following substeps: (e.1) depositing a layer of polysilicon, (e.2) depositing a layer of metal-silicide, (e.3) depositing a dielectric layer, and (e.4) etching the dielectric layer, the layer of metal-silicide and the layer of polysilicon to form the first transistor gate; and, (f) after forming the first transistor gate within the second region etching the gate material which is over the first region to form a second transistor gate.

Claim 7

A method comprising the following steps: (a) forming gate oxide within regions on a substrate; (b) forming gate material over a first region, the gate material extending over field oxide surrounding the first region; (c) stripping gate oxide within a second region, the gate material over the first region preventing gate oxide within the first region from being stripped; (d) forming a new layer of gate oxide within the second region; (e) forming a first transistor gate within the second region, including the following substeps: (e.1) depositing a layer of polysilicon, (e.2) depositing a layer of metal-silicide, (e.3) depositing a dielectric layer, and (e.4) etching the dielectric layer, the layer of metal-silicide and the layer of polysilicon to form the first transistor gate; and, (f) after forming the first transistor gate within the second region etching the gate material which is over the first region to form a second transistor gate.

Claim 11

A method comprising the following steps: (a) on a substrate, forming separate regions, the regions being separated by field oxide; (b) forming gate oxide within the regions; (c) forming polysilicon over a first region, the polysilicon extending over field oxide surrounding the first region; (d) stripping gate oxide within a second region, the polysilicon over the first region preventing gate oxide within the first region from being stripped; (e) forming a new layer of gate oxide within the second region; (f) forming a first transistor gate within the second region, including the following substeps: (f.1) depositing a layer of polysilicon, (f.2) depositing a layer of metal-silicide, (f.3) depositing a dielectric layer, and (f.4) etching the dielectric layer, the layer of metal-silicide and the layer of polysilicon to form the first transistor gate; (g) placing resist masking over the second region, over the first transistor gate within the second region and over a portion of the polysilicon over the first region; (h) etching the polysilicon which is over the first region to form a second transistor gate, the transistor gate consisting of the portion of the polysilicon under the resist masking; and, (i) removing the resist masking.

Claim 12

A method comprising the following steps: (a) on a substrate, forming separate regions, the regions being separated by field oxide; (b) forming gate oxide within the regions; (c) forming polysilicon over a first region, the polysilicon extending over field oxide surrounding the first region; (d) stripping gate oxide within a second region, the polysilicon over the first region preventing gate oxide within the first region from being stripped; (e) forming a new layer of gate oxide within the second region; (f) forming a first transistor gate within the second region, including the following substeps: (f.1) depositing a layer of polysilicon, (f.2) depositing a layer of metal-silicide, (f.3) depositing a dielectric layer, and (f.4) etching the dielectric layer, the layer of metal-silicide and the layer of polysilicon to form the first transistor gate; (g) placing resist masking over the second region, over the first transistor gate within the second region and over a portion of the polysilicon over the first region; (h) etching the polysilicon which is over the first region to form a second transistor gate, the transistor gate consisting of the portion of the polysilicon under the resist masking; and, (i) removing the resist masking.

Claim 14

A method comprising the following steps: (a) forming gate oxide within regions on a substrate; (b) forming polysilicon over a first region, the polysilicon extending over field oxide surrounding the first region; (c) thinning gate oxide within a second region, the polysilicon over the first region preventing gate oxide within the first region from being thinned; (d) forming a first transistor gate within the second region and a capacitor top electrode within the first region; and, (e) after the first transistor gate is formed within the second region and the capacitor top electrode is formed within the first region, etching the polysilicon which is over the first region to form a capacitor bottom electrode.

Claim 15

A method comprising the following steps: (a) forming gate oxide within regions on a substrate; (b) forming polysilicon over a first region, the polysilicon extending over field oxide surrounding the first region; (c) thinning gate oxide within a second region, the polysilicon over the first region preventing gate oxide within the first region from being thinned; (d) forming a first transistor gate within the second region and a capacitor top electrode within the first region; and, (e) after the first transistor gate is formed within the second region and the capacitor top electrode is formed within the first region, etching the polysilicon which is over the first region to form a capacitor bottom electrode.