US6368947B1
Expired / Lapsed
US
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Process utilizing a cap layer optimized to reduce gate line over-melt
Assignee: GlobalFoundries Inc
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Filing: 2000-06-20
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Granted: 2002-04-09
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Expires: 2020-06-20
Abstract
Abstract A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-40 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).
Inventors
- 👤 Bin Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:09
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10P30/208; H10P30/225; H10P34/00; H10P34/40; H10P34/42
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
139 words
A method of manufacturing an integrated circuit, comprising: forming at least a portion of a gate structure including a polysilicon gate conductor and a cap layer, the gate structure being disposed on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous region near the top surface of the substrate; first doping the substrate for drain and source extensions; providing oxide spacers, the spacers abutting the gate conductor; providing a second amorphization implant, the second amorphization implant creating a deep, second amorphous region in the substrate; second doping the substrate to form deep source and drain regions; removing the cap layer to expose the polysilicon gate conductor; and thermally annealing the substrate to melt the first amorphous region, the second amorphous region and a portion of the gate conductor.
Claim 2
Independent Claim
139 words
A method of manufacturing an integrated circuit, comprising: forming at least a portion of a gate structure including a polysilicon gate conductor and a cap layer, the gate structure being disposed on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous region near the top surface of the substrate; first doping the substrate for drain and source extensions; providing oxide spacers, the spacers abutting the gate conductor; providing a second amorphization implant, the second amorphization implant creating a deep, second amorphous region in the substrate; second doping the substrate to form deep source and drain regions; removing the cap layer to expose the polysilicon gate conductor; and thermally annealing the substrate to melt the first amorphous region, the second amorphous region and a portion of the gate conductor.
Claim 3
Dependent Claim
18 words
The method of claim 1 , wherein the deep amorphous region is 150-200 nm below the top surface.
Claim 4
Dependent Claim
17 words
The method of claim 2 , wherein the first amorphous region is 10-15 nm below the surface.
Claim 5
Dependent Claim
21 words
The method of claim 1 , further comprising: providing an insulative layer over the gate structure after the second amorphization implant.
Claim 6
Independent Claim
150 words
A method of manufacturing an integrated circuit, comprising: forming at least a portion of a gate structure including a polysilicon gate conductor and a cap layer, the gate structure being disposed on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous region near the top surface of the substrate; first doping the substrate for drain and source extensions; providing oxide spacers, the spacers abutting the gate conductor; providing a second amorphization implant, the second amorphization implant creating a deep amorphous region in the substrate; second doping the substrate to form deep source and drain regions; providing an insulative layer over the gate structure after the second amorphization implant; polishing the insulative layer to expose the cap layer; and thermally annealing the substrate to melt the first amorphous region, the second amorphous region and a portion of the gate conductor.
Claim 7
Independent Claim
150 words
A method of manufacturing an integrated circuit, comprising: forming at least a portion of a gate structure including a polysilicon gate conductor and a cap layer, the gate structure being disposed on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous region near the top surface of the substrate; first doping the substrate for drain and source extensions; providing oxide spacers, the spacers abutting the gate conductor; providing a second amorphization implant, the second amorphization implant creating a deep amorphous region in the substrate; second doping the substrate to form deep source and drain regions; providing an insulative layer over the gate structure after the second amorphization implant; polishing the insulative layer to expose the cap layer; and thermally annealing the substrate to melt the first amorphous region, the second amorphous region and a portion of the gate conductor.
Claim 8
Dependent Claim
17 words
The method of claim 5 , further comprising: removing the cap layer before the thermally annealing step.
Claim 9
Dependent Claim
19 words
The method of claim 6 , wherein the providing the spacers step is performed after the first doping step.
Claim 10
Dependent Claim
17 words
The method of claim 1 further comprising: providing the first amorphization implant before the first doping step.
Claim 11
Dependent Claim
15 words
The method of claim 1 , wherein the annealing step is a laser annealing step.
Claim 12
Independent Claim
177 words
A method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions, the method comprising steps of: forming at least part of a gate structure including a gate conductor above a top surface of a semiconductor substrate and a cap layer above the gate conductor; providing a shallow amorphization implant, the shallow amorphization implant creating a shallow amorphous region near the top surface; first doping the substrate to form the shallow source and drain extensions; providing spacers, the spacers abutting the gate structures; providing a deep amorphization implant, the deep amorphization implant creating a deep amorphous region in the substrate; second doping the substrate to form source and drain regions; providing an insulative layer over the gate structures; removing a portion of the insulative layer to expose the cap layer; and laser annealing the substrate to melt the shallow amorphous region, the deep amorphous region and a portion of the gate conductor, thereby forming shallow source and drain extensions having a thickness of less than 30 nm.
Claim 13
Independent Claim
177 words
A method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions, the method comprising steps of: forming at least part of a gate structure including a gate conductor above a top surface of a semiconductor substrate and a cap layer above the gate conductor; providing a shallow amorphization implant, the shallow amorphization implant creating a shallow amorphous region near the top surface; first doping the substrate to form the shallow source and drain extensions; providing spacers, the spacers abutting the gate structures; providing a deep amorphization implant, the deep amorphization implant creating a deep amorphous region in the substrate; second doping the substrate to form source and drain regions; providing an insulative layer over the gate structures; removing a portion of the insulative layer to expose the cap layer; and laser annealing the substrate to melt the shallow amorphous region, the deep amorphous region and a portion of the gate conductor, thereby forming shallow source and drain extensions having a thickness of less than 30 nm.
Claim 14
Dependent Claim
21 words
The method of claim 10 , further comprising removing the cap layer above the gate conductor before the laser annealing step.
Claim 15
Dependent Claim
14 words
The method of claim 10 , wherein the laser annealing is excimer laser annealing.
Claim 16
Dependent Claim
12 words
The method of claim 10 , wherein the gate conductor includes polysilicon.
Claim 17
Dependent Claim
24 words
The method of claim 13 , wherein the dopant concentration of the source and drain regions is above 10 21 dopants per cubic centimeter.
Claim 18
Dependent Claim
18 words
The method of claim 10 , wherein the portion includes between 50 and 66% of the gate conductor.
Claim 19
Independent Claim
203 words
A method of providing a plurality of ultra-shallow drain/source extensions for field effect transistors associated with an ultra-large scale integrated circuit, the method comprising: forming a plurality of at least a portion of gate structures including capped gate conductors on a top surface of a silicon substrate, the capped gate conductors including a gate conductor layer below a cap layer; providing a first amorphization implant, the first amorphization implant creating a first amorphous semiconductor region near the top surface of the substrate; first doping the substrate in the first amorphous semiconductor region for the ultra-shallow drain/source extensions; providing spacers, the spacers abutting the gate structures; providing a second amorphization implant, the second amorphization implant creating a deep amorphous semiconductor region in the substrate; second doping the substrate in the deep amorphous semiconductor region to form source and drain regions; providing an insulative layer above the capped gate structures; removing at least a portion of the insulative layer and the cap layer to expose the gate conductor layer; and thermally annealing the substrate to form the ultra shallow drain/source extensions, wherein the thermally annealing step melts the first amorphous semiconductor region, the deep amorphous semiconductor region and a portion of the gate conductor layer.
Claim 20
Independent Claim
203 words
A method of providing a plurality of ultra-shallow drain/source extensions for field effect transistors associated with an ultra-large scale integrated circuit, the method comprising: forming a plurality of at least a portion of gate structures including capped gate conductors on a top surface of a silicon substrate, the capped gate conductors including a gate conductor layer below a cap layer; providing a first amorphization implant, the first amorphization implant creating a first amorphous semiconductor region near the top surface of the substrate; first doping the substrate in the first amorphous semiconductor region for the ultra-shallow drain/source extensions; providing spacers, the spacers abutting the gate structures; providing a second amorphization implant, the second amorphization implant creating a deep amorphous semiconductor region in the substrate; second doping the substrate in the deep amorphous semiconductor region to form source and drain regions; providing an insulative layer above the capped gate structures; removing at least a portion of the insulative layer and the cap layer to expose the gate conductor layer; and thermally annealing the substrate to form the ultra shallow drain/source extensions, wherein the thermally annealing step melts the first amorphous semiconductor region, the deep amorphous semiconductor region and a portion of the gate conductor layer.
Claim 21
Dependent Claim
22 words
The method of claim 16 , wherein the ultra-shallow drain/source extensions have a dopant concentration above 10 21 dopants per cubic centimeter.
Claim 22
Dependent Claim
36 words
The method of claim 17 , wherein the first amorphous semiconductor region is less than 10-15 nm below the top surface, and the deep amorphous semiconductor region is more than 150-200 nm below the top surface.
Claim 23
Dependent Claim
17 words
The method of claim 18 , wherein the thermal annealing is performed by laser annealing the substrate.
Claim 24
Independent Claim
167 words
A method of providing a plurality of ultra-shallow drain/source extensions for field effect transistors associated with an ultra-large scale integrated circuit, the method comprising: forming a plurality of at least a portion of gate structures including capped gate conductors on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous semiconductor region near the top surface of the substrate; doping the substrate for the drain/source extensions; providing spacers, the spacers abutting the gate structures; providing a second amorphization implant, the second amorphization implant creating a deep amorphous semiconductor region in the substrate; doping the substrate to form source and drain regions; providing an insulative layer above the gate structures; removing a portion of the insulative layer to expose the capped gate conductors; and thermally annealing the substrate to form the ultra shallow drain/source extensions, wherein the thermally annealing step melts the first amorphous semiconductor region, the deep amorphous semiconductor region and a portion of the gate conductors.
Claim 25
Independent Claim
167 words
A method of providing a plurality of ultra-shallow drain/source extensions for field effect transistors associated with an ultra-large scale integrated circuit, the method comprising: forming a plurality of at least a portion of gate structures including capped gate conductors on a top surface of a silicon substrate; providing a first amorphization implant, the first amorphization implant creating a first amorphous semiconductor region near the top surface of the substrate; doping the substrate for the drain/source extensions; providing spacers, the spacers abutting the gate structures; providing a second amorphization implant, the second amorphization implant creating a deep amorphous semiconductor region in the substrate; doping the substrate to form source and drain regions; providing an insulative layer above the gate structures; removing a portion of the insulative layer to expose the capped gate conductors; and thermally annealing the substrate to form the ultra shallow drain/source extensions, wherein the thermally annealing step melts the first amorphous semiconductor region, the deep amorphous semiconductor region and a portion of the gate conductors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-08 | 2005-10-08 | 2006-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-08 | 2009-10-08 | 2010-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-08 | 2013-10-08 | 2014-04-09 | $7700.00 | Window Closed / Lapsed |