EEPROM cell and related method of making thereof

Claim 1

The method for fabricating an EEPROM cell comprising the steps of: forming a first insulation film on a semiconductor substrate having a first conductivity type and a surface; forming a first photoresist film on said first insulation film; patterning said first photoresist film to expose first and second portions of said first insulation film by a photoetching process; forming a source region having a second conductivity type by implanting impurities into said substrate through said exposed first portion of said first insulation film using said first photoresist film as a mask, said source region having a predetermined junction depth; forming a drain region having said second conductivity type by implanting impurities into said substrate through said exposed second portion of said first insulation film using said first photoresist film as said mask, said drain region having said predetermined junction depth; forming a trench by etching said substrate between source and drain regions and etching portions of said source and drain region; forming first and second spacers on sidewalls of said trench by coating a second insulation film over said surface of said substrate and anisotropically etching said second insulation film, said first spacer being adjacent said drain region and said second spacer is adjacent said source region; forming a gate oxide film on a bottom of said trench between said first and second spacers; forming a tunneling oxide film over said drain region adjacent said first spacer; forming a floating gate on said first insulation film overlying said source and drain region, said floating gate being formed on said tunneling oxide film and in said trench, said step of forming said floating gate including the steps of coating a film on said surface of substrate and patterning said film; forming third and fourth spacers on said first insulation film at side surfaces, of said floating gate by providing a third insulation film on said surface of said substrate and anisotropically etching said third insulation film; forming a capacitor dielectric film on said floating gate and said third and fourth spacers; and forming a control gate on said dielectric film.

Claim 2

The method for fabricating an EEPROM cell comprising the steps of: forming a first insulation film on a semiconductor substrate having a first conductivity type and a surface; forming a first photoresist film on said first insulation film; patterning said first photoresist film to expose first and second portions of said first insulation film by a photoetching process; forming a source region having a second conductivity type by implanting impurities into said substrate through said exposed first portion of said first insulation film using said first photoresist film as a mask, said source region having a predetermined junction depth; forming a drain region having said second conductivity type by implanting impurities into said substrate through said exposed second portion of said first insulation film using said first photoresist film as said mask, said drain region having said predetermined junction depth; forming a trench by etching said substrate between source and drain regions and etching portions of said source and drain region; forming first and second spacers on sidewalls of said trench by coating a second insulation film over said surface of said substrate and anisotropically etching said second insulation film, said first spacer being adjacent said drain region and said second spacer is adjacent said source region; forming a gate oxide film on a bottom of said trench between said first and second spacers; forming a tunneling oxide film over said drain region adjacent said first spacer; forming a floating gate on said first insulation film overlying said source and drain region, said floating gate being formed on said tunneling oxide film and in said trench, said step of forming said floating gate including the steps of coating a film on said surface of substrate and patterning said film; forming third and fourth spacers on said first insulation film at side surfaces, of said floating gate by providing a third insulation film on said surface of said substrate and anisotropically etching said third insulation film; forming a capacitor dielectric film on said floating gate and said third and fourth spacers; and forming a control gate on said dielectric film.