Semiconductor memory device with selection gate in a groove

Claim 2

A semiconductor memory device, comprising: a semiconductor substrate of a first conductivity type; first and second impurity diffusion layers of a second conductivity type formed in said semiconductor substrate with a first preset distance therebetween; a selection gate electrode formed over that area of said semiconductor substrate between said first and second impurity diffusion layers, said selection gate electrode being formed in a groove which is formed in a portion of said semiconductor substrate between said first and second impurity diffusion layers; a third impurity diffusion layer of said second conductivity type formed in an area of said semiconductor substrate which is different from the area between said first and second impurity diffusion layers and is at a second preset distance from said first impurity diffusion layer; a first gate oxide film formed on the area of said semiconductor substrate between said first and second impurity diffusion layers and an area of said semiconductor substrate between said first and third impurity diffusion layers, formed to be at least partly superposed on said selection gate electrode and having a tunnel oxide film formed on said first impurity diffusion layer; a floating gate electrode formed on portions of said first gate oxide film which lie over the area of said semiconductor substrate between said first and second impurity diffusion layers and the area of said semiconductor substrate between said second and third impurity diffusion layers and formed to be at least partly disposed over said selection gate electrode; a second gate oxide film formed on said floating gate electrode; and a control gate electrode formed over said floating gate electrode with said second gate oxide film disposed therebetween.

Claim 3

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; an element isolation region formed on said semiconductor substrate to divide said semiconductor substrate into said and second element regions; first and second impurity diffusion layers of a second conductivity type formed at a preset distance from each other in said first element region; a selection gate electrode formed over that area of said first element region between said first and second impurity diffusion layers, said selection gate electrode being formed in a groove which is formed in a portion of said semiconductor substrate lying between first and second impurity diffusion layers; a third impurity diffusion layer of said second conductivity type formed at a preset distance from said first impurity diffusion layer and formed in an area of said first element region different from the area between said first and second impurity diffusion layers; a first gate oxide film formed on the area of said first element region between said first and second impurity diffusion layers and the area of said first element region between said first and third impurity diffusion layers, formed to be at least partly superposed on said selection gate electrode, and having a tunnel oxide film formed on said first impurity diffusion layer; a floating gate electrode formed on portions of said first gate oxide film over the area of said first element region between said first and second impurity diffusion layers and the area of said first element region lying between said first and third impurity diffusion layers and formed to be at least partly disposed over said selection gate electrode; a second gate oxide film formed on said second element region of said semiconductor substrate; and a control gate electrode formed on said second gate oxide film and formed to be electrically connected to said floating gate electrode.

Claim 4

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; an element isolation region formed on said semiconductor substrate to divide said semiconductor substrate into said and second element regions; first and second impurity diffusion layers of a second conductivity type formed at a preset distance from each other in said first element region; a selection gate electrode formed over that area of said first element region between said first and second impurity diffusion layers, said selection gate electrode being formed in a groove which is formed in a portion of said semiconductor substrate lying between first and second impurity diffusion layers; a third impurity diffusion layer of said second conductivity type formed at a preset distance from said first impurity diffusion layer and formed in an area of said first element region different from the area between said first and second impurity diffusion layers; a first gate oxide film formed on the area of said first element region between said first and second impurity diffusion layers and the area of said first element region between said first and third impurity diffusion layers, formed to be at least partly superposed on said selection gate electrode, and having a tunnel oxide film formed on said first impurity diffusion layer; a floating gate electrode formed on portions of said first gate oxide film over the area of said first element region between said first and second impurity diffusion layers and the area of said first element region lying between said first and third impurity diffusion layers and formed to be at least partly disposed over said selection gate electrode; a second gate oxide film formed on said second element region of said semiconductor substrate; and a control gate electrode formed on said second gate oxide film and formed to be electrically connected to said floating gate electrode.

Claim 5

The semiconductor memory device according to claim 1, wherein said second impurity diffusion layer is formed with an LDD structure.

Claim 6

The semiconductor memory device according to claim 1, wherein the thickness of a portion of said first gate oxide film formed on said selection gate electrode is greater than the thickness of a portion of said first gate oxide film formed on said semiconductor substrate.

Claim 7

The semiconductor memory device according to claim 4, wherein a capacitance between said portion of said first gate oxide film formed on said selection gate electrode and said selection gate electrode is different than a capacitance between said portion of said first gate oxide film formed on said semiconductor substrate and said semiconductor substrate.

Claim 8

The semiconductor memory device according to claim 2, wherein said second impurity diffusion layer is formed with an LDD structure.

Claim 9

The semiconductor memory device according to claim 2, wherein the thickness of a portion of said first gate oxide film formed on said selection gate electrode is greater than the thickness of a portion of said first gate oxide film formed on said semiconductor substrate.

Claim 10

The semiconductor memory device according to claim 7, wherein a capacitance between said portion of said first gate oxide film formed on said selection gate electrode and said selection gate electrode is different than a capacitance between said portion of said first gate oxide film formed on said semiconductor substrate and said semiconductor substrate.

Claim 11

A semiconductor memory device, comprising: a body of semiconductor material of a first conductivity type having a major surface; first, second, and third regions of a second conductivity type formed in said major surface of said semiconductor body; a conductive layer insulatively spaced from a channel region between said first and second regions; a floating gate electrode for storing charge; a first insulating film portion for insulating said floating gate from a channel region between said second and third regions; a second insulating film portion for insulating said floating gate from said conductive layer, said second insulating film portion having a thickness greater than a thickness of said first insulating film portion; a control gate electrode; and a groove formed in said major surface of said semiconductor body between said first and second regions, said groove having sidewalls and a bottom wall, wherein at least a portion of said conductive layer is formed in said groove and said conductive layer is insulatively spaced from said channel region between said first and second regions by an insulating film formed on said bottom wall of said groove.

Claim 12

A semiconductor memory device, comprising: a body of semiconductor material of a first conductivity type having a major surface; first, second, and third regions of a second conductivity type formed in said major surface of said semiconductor body; a conductive layer insulatively spaced from a channel region between said first and second regions; a floating gate electrode for storing charge; a first insulating film portion for insulating said floating gate from a channel region between said second and third regions; a second insulating film portion for insulating said floating gate from said conductive layer, said second insulating film portion having a thickness greater than a thickness of said first insulating film portion; a control gate electrode; and a groove formed in said major surface of said semiconductor body between said first and second regions, said groove having sidewalls and a bottom wall, wherein at least a portion of said conductive layer is formed in said groove and said conductive layer is insulatively spaced from said channel region between said first and second regions by an insulating film formed on said bottom wall of said groove.

Claim 13

The semiconductor memory device according to claim 9, wherein a top surface of said conductive layer is substantially coplanar with said major surface of said semiconductor body.

Claim 14

The semiconductor memory device according to claim 9, wherein portions of said first and second regions extend under said groove.