Non-volatile semiconductor memory device using contact hole connection

Claim 2

A non-volatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having a major surface; and a plurality of memory transistors commmonly formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory transistors including: first, second, and third impurity regions of a second conductivity type opposite said first conductivity type formed spaced apart on said major surface of said semiconductor substrate with a first prescribed space between said first and second impurity regions forming a first channel region and a second prescribed space between said second and third impurity regions defining a second channel region, said channel regions formed in portions of said major surface of said semiconductor substrate, a first conductor formed on said second channel region through a first insulating film, a second conductor formed on said first channel region through an insulating film and on said first conductor through a second insulating film, and a third conductor formed on said second conductor through an insulating film and electrically connected to said first conductor through a contact hole formed in said second insulating film, said third impurity region being connected to said common source line.

Claim 3

A non-volatile semiconductor memory device in accordance with claim 1, wherein an interlayer isolation film is formed on said third impurity region.

Claim 4

A non-volatile semiconductor memory device in accordance with claim 1, further comprising: a plurality of select gate transistors provided in correspondence to respective ones of said memory transistors, each of said plurality of select gate transistors including: a fourth impurity region of said second conductivity type, being reverse to said first conductivity type, formed on said major surface of said semiconductor substrate with a prescribed space from said first impurity region to define a third channel region in a portion of said major surface of said semiconductor substrate held between the same and said first impurity region, and a fourth conductor formed on said third channel region through an insulating film.

Claim 5

A non-volatile semiconductor memory device in accordance with claim 3, wherein said second conductor is also formed on said fourth conductor through an insulating film, and said third conductor is also formed above said fourth conductor.

Claim 6

A non-volatile semiconductor memory device in accordance with claim 4, wherein said fourth impurity region is connected to a bit line, and said fourth conductor is connected to a word line.

Claim 7

A non-volatile semiconductor memory device, comprising: a semiconductor substrate of a first conductivity type and having a major surface; and a plurality of memory transistors commonly formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory transistors including: (a) first, second and third impurity regions of a second conductivity type, opposite that of said first conductivity type, formed on said major surface of said semiconductor substrate with prescribed spaces to define first and second channel regions in portions of said major surface of said semiconductor substrate therebetween, (b) a first control gate formed on said second channel region through a first insulating film in alignment with said third impurity region, (c) a floating gate formed on said first channel region through a second insulating film and on said first control gate through a third insulating film, said floating gate extending over a portion of said second channel region, whereby said floating gate is electrically shielded from said third impurity region by said first control gate, and (d) a second control gate formed on the floating gate through an insulating film and electrically connected to said first control gate through a contact hole formed in said third insulating film; said third impurity region being connected to said common source line.

Claim 8

A non-volatile semiconductor memory device, comprising: a semiconductor substrate of a first conductivity type and having a major surface; and a plurality of memory transistors commonly formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory transistors including: (a) first, second and third impurity regions of a second conductivity type, opposite that of said first conductivity type, formed on said major surface of said semiconductor substrate with prescribed spaces to define first and second channel regions in portions of said major surface of said semiconductor substrate therebetween, (b) a first control gate formed on said second channel region through a first insulating film in alignment with said third impurity region, (c) a floating gate formed on said first channel region through a second insulating film and on said first control gate through a third insulating film, said floating gate extending over a portion of said second channel region, whereby said floating gate is electrically shielded from said third impurity region by said first control gate, and (d) a second control gate formed on the floating gate through an insulating film and electrically connected to said first control gate through a contact hole formed in said third insulating film; said third impurity region being connected to said common source line.

Claim 9

A non-volatile semiconductor memory device in accordance with claim 1, wherein said plurality of memory transistors connected to said common source line form at least one byte, and respective said third impurity regions of said memory transistors forming said one byte are interconnected with each other to be connected to said common source line.

Claim 10

A non-volatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having a major surface; and a plurality of memory transistors commonly formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory transistors including: first, second, and third impurity regions of a second conductivity type opposite said first conductivity type formed spaced apart on said major surface of said semiconductor substrate, said first and third impurity regions formed on opposite sides of said second impurity region with a first predetermined space between said first and second impurity regions defining a first channel region in said major surface of said semiconductor substrate and a second predetermined space between said second and third impurity regions defining a second channel region in said major surface of said semiconductor substrate, said third impurity region electrically connected to said common source line; first and second insulating films formed on said major surface of said substrate on first and second channel regions, respectively; a first control electrode formed on said second insulating film over said second channel region; a third insulating film formed on said first control electrode; a floating gate having a vertical portion formed on said first insulating film over said first channel region and a horizontal portion formed on said third insulating film and extending over said first control electrode; a fourth insulating film formed on said horizontal portion of said floating gate; and a second control electrode formed on said fourth insulating film over said floating gate and electrically connected to said first control electrode.

Claim 11

A non-volatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having a major surface; and a plurality of memory transistors commonly formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory transistors including: first, second, and third impurity regions of a second conductivity type opposite said first conductivity type formed spaced apart on said major surface of said semiconductor substrate, said first and third impurity regions formed on opposite sides of said second impurity region with a first predetermined space between said first and second impurity regions defining a first channel region in said major surface of said semiconductor substrate and a second predetermined space between said second and third impurity regions defining a second channel region in said major surface of said semiconductor substrate, said third impurity region electrically connected to said common source line; first and second insulating films formed on said major surface of said substrate on first and second channel regions, respectively; a first control electrode formed on said second insulating film over said second channel region; a third insulating film formed on said first control electrode; a floating gate having a vertical portion formed on said first insulating film over said first channel region and a horizontal portion formed on said third insulating film and extending over said first control electrode; a fourth insulating film formed on said horizontal portion of said floating gate; and a second control electrode formed on said fourth insulating film over said floating gate and electrically connected to said first control electrode.

Claim 12

A non-volatile semiconductor memory device in accordance with claim 8, wherein said second control electrode is electrically connected to said first conductor through a contact hole formed in said third insulating film.

Claim 13

A non-volatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having a major surface; a plurality of bit lines; and a plurality of memory cells formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory cells including: first, second third and fourth impurity regions of a second conductivity type opposite said first conductivity type formed spaced apart on said major surface of said semiconductor substrate, said first and third impurity regions formed on opposite sides of said second impurity region and said fourth impurity region formed on the side of said third impurity region opposite said second impurity region, said first impurity region electrically connected to one of said bit liens and said fourth impurity region electrically connected to said common source line, a first predetermined portion of said substrate between said first and second impurity regions constituting a first channel region, a second predetermined portion of said substrate between said second and third impurity regions constituting a second channel region, a third predetermined portion of said substrate between said third and fourth impurity regions constituting a third channel region, a first insulating film formed on said major surface of said substrate on said first and third channel regions, a second insulating film formed on said major surface of said substrate on said second channel region, a select gate electrode formed on said first insulating film over said first channel region, a first control electrode formed on said first insulating film over said third channel region, a third insulating film formed on said select gate electrode and on first control electrode, a floating gate having a lower vertical portion formed on said second insulating film over said second channel region and an upper horizontal portion formed on said third insulating film and extending over said select gate and first control gate electrodes, a fourth insulating film formed on said floating gate, and a second control electrode formed on said fourth insulating film over said floating gate and electrically connected to said first conductor.

Claim 14

A non-volatile semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having a major surface; a plurality of bit lines; and a plurality of memory cells formed on said major surface of said semiconductor substrate and connected to a common source line, each of said plurality of memory cells including: first, second third and fourth impurity regions of a second conductivity type opposite said first conductivity type formed spaced apart on said major surface of said semiconductor substrate, said first and third impurity regions formed on opposite sides of said second impurity region and said fourth impurity region formed on the side of said third impurity region opposite said second impurity region, said first impurity region electrically connected to one of said bit liens and said fourth impurity region electrically connected to said common source line, a first predetermined portion of said substrate between said first and second impurity regions constituting a first channel region, a second predetermined portion of said substrate between said second and third impurity regions constituting a second channel region, a third predetermined portion of said substrate between said third and fourth impurity regions constituting a third channel region, a first insulating film formed on said major surface of said substrate on said first and third channel regions, a second insulating film formed on said major surface of said substrate on said second channel region, a select gate electrode formed on said first insulating film over said first channel region, a first control electrode formed on said first insulating film over said third channel region, a third insulating film formed on said select gate electrode and on first control electrode, a floating gate having a lower vertical portion formed on said second insulating film over said second channel region and an upper horizontal portion formed on said third insulating film and extending over said select gate and first control gate electrodes, a fourth insulating film formed on said floating gate, and a second control electrode formed on said fourth insulating film over said floating gate and electrically connected to said first conductor.

Claim 15

A non-volatile semiconductor memory device in accordance with claim 10, wherein said second control electrode is electrically connected to said first control electrode through a contact hole formed in said second insulating film.