US5583360A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertically formed neuron transister having a floating gate and a control gate
Assignee: NXP USA Inc
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Filing: 1995-08-28
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Granted: 1996-12-10
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Expires: 2015-08-28
Abstract
Abstract A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
Inventors
- 👤 Scott S. Roth
- 👤 William C. McFadden
- 👤 Alexander J. Pepe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:24
CPC Classifications
H; H10; H10B; H10B41/00; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/972
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
139 words
A transistor comprising: a substrate; a source region and a drain region within the substrate wherein the source region is separated from the drain region by a channel region; a floating gate overlying the channel region, the floating gate having a bottom surface for controlling a conductivity of the channel region and a sidewall surface; and N control gates laterally adjacent the sidewall surface of the floating gate wherein N is a positive integer greater than zero, each of the N control gates selectively altering the conductivity of the channel region by capacitive coupling, to the sidewall of the floating gate, voltages applied to each of the N control gates through the floating gate wherein each voltage provided by each of the N control gates is independent from all other voltages provided by other of the N control gates.
Claim 2
Dependent Claim
139 words
A transistor comprising: a substrate; a source region and a drain region within the substrate wherein the source region is separated from the drain region by a channel region; a floating gate overlying the channel region, the floating gate having a bottom surface for controlling a conductivity of the channel region and a sidewall surface; and N control gates laterally adjacent the sidewall surface of the floating gate wherein N is a positive integer greater than zero, each of the N control gates selectively altering the conductivity of the channel region by capacitive coupling, to the sidewall of the floating gate, voltages applied to each of the N control gates through the floating gate wherein each voltage provided by each of the N control gates is independent from all other voltages provided by other of the N control gates.
Claim 3
Dependent Claim
70 words
The transistor of claim 1 wherein the N control gates are defined by M conductive layers overlying the substrate, where M is a positive integer, the M conductive layers being rank ordered wherein each of the M conductive layers which has a rank greater than one overlies a conductive layer having an immediate lower rank, each of the M conductive layers forming at least one of said N control gates.
Claim 4
Dependent Claim
11 words
The transistor of claim 2 wherein N is equal to M.
Claim 5
Dependent Claim
30 words
The transistor of claim 1 further comprising: a conductive layer overlying the substrate, the conductive layer having an opening which physically separates the conductive layer into said N control gates.
Claim 6
Dependent Claim
14 words
The transistor of claim 4 wherein said floating gate is formed within said opening.
Claim 7
Dependent Claim
28 words
The transistor of claim 1 further comprising: a vertical sidewall formed from each of the N control gates, wherein each vertical sidewall is positioned adjacent the floating gate.
Claim 8
Dependent Claim
193 words
A transistor formed overlying a substrate having a top surface, the transistor comprising: a source within the substrate; a drain within the substrate; a channel region within the substrate, the channel region lying between the source and the drain and capable of conducting a horizontal current flow parallel to the top surface of the substrate between the source and drain; a gate dielectric layer adjacent the channel region; a conductive floating gate overlying the gate dielectric layer, the conductive floating gate having a vertical sidewall; a sidewall dielectric layer formed adjacent the vertical sidewall of the conductive floating gate; and a conductive control electrode laterally adjacent the vertical sidewall of the conductive floating gate, the conductive control electrode having a sidewall portion wherein the sidewall portion of the conductive control electrode is facing the vertical sidewall portion of the conductive floating gate wherein the sidewall portion of the conductive control electrode and the vertical sidewall portion of the conductive floating gate are capacitively coupled through the sidewall dielectric layer, a conductivity of the channel region being altered by capacitive coupling between the conductive control electrode and the conductive floating gate the floating gate.
Claim 9
Dependent Claim
193 words
A transistor formed overlying a substrate having a top surface, the transistor comprising: a source within the substrate; a drain within the substrate; a channel region within the substrate, the channel region lying between the source and the drain and capable of conducting a horizontal current flow parallel to the top surface of the substrate between the source and drain; a gate dielectric layer adjacent the channel region; a conductive floating gate overlying the gate dielectric layer, the conductive floating gate having a vertical sidewall; a sidewall dielectric layer formed adjacent the vertical sidewall of the conductive floating gate; and a conductive control electrode laterally adjacent the vertical sidewall of the conductive floating gate, the conductive control electrode having a sidewall portion wherein the sidewall portion of the conductive control electrode is facing the vertical sidewall portion of the conductive floating gate wherein the sidewall portion of the conductive control electrode and the vertical sidewall portion of the conductive floating gate are capacitively coupled through the sidewall dielectric layer, a conductivity of the channel region being altered by capacitive coupling between the conductive control electrode and the conductive floating gate the floating gate.
Claim 10
Dependent Claim
84 words
The transistor of claim 7 wherein a plurality of control gates is defined by M conductive layers overlying the substrate, where M is a positive integer, and the plurality of the control gates includes said conductive control gate, the M conductive layers being rank ordered wherein each of the M conductive layers which has a rank greater than one overlies a conductive layer having an immediate lower rank, each of the M conductive layers forming at least one of said plurality of control gates.
Claim 11
Dependent Claim
27 words
The transistor of claim 7 further comprising: N conductive polysilicon segments overlying the substrate wherein one of the N conductive polysilicon segments forms the conductive control electrode.
Claim 12
Dependent Claim
37 words
The transistor of claim 7 further comprising: a conductive layer overlying the substrate, the conductive layer having an opening which physically separates the conductive layer into a plurality of control gates which includes said conductive control gate.
Claim 13
Dependent Claim
141 words
A transistor comprising: a substrate; a source region formed within the substrate; a drain region formed within the substrate; a channel region within the substrate and separating the source region from the drain region; a first conductive layer overlying the substrate; a second conductive layer overlying the first conductive layer; an opening formed through the first conductive layer and the second conductive layer to form at least two control gate electrodes from the first and second conductive layers, the opening forming sidewalls of the at least two control gate electrodes; a floating gate electrode within the opening, laterally adjacent the sidewalls of the at least two control gate electrodes, and overlying the channel region such that voltages placed upon the at least two control gate electrodes alters a current through the channel region via capacitive coupling through the floating gate electrode.
Claim 14
Dependent Claim
141 words
A transistor comprising: a substrate; a source region formed within the substrate; a drain region formed within the substrate; a channel region within the substrate and separating the source region from the drain region; a first conductive layer overlying the substrate; a second conductive layer overlying the first conductive layer; an opening formed through the first conductive layer and the second conductive layer to form at least two control gate electrodes from the first and second conductive layers, the opening forming sidewalls of the at least two control gate electrodes; a floating gate electrode within the opening, laterally adjacent the sidewalls of the at least two control gate electrodes, and overlying the channel region such that voltages placed upon the at least two control gate electrodes alters a current through the channel region via capacitive coupling through the floating gate electrode.
Claim 15
Dependent Claim
36 words
The transistor of claim 11 wherein the opening segments the first conductive layer into a first control gate electrode and a second control gate electrode which are part of the at least two control gate electrodes.
Claim 16
Dependent Claim
36 words
The transistor of claim 11 wherein the opening segments the second conductive layer into a first control gate electrode and a second control gate electrode which are part of the at least two control gate electrodes.
Claim 17
Dependent Claim
28 words
The transistor of claim 11 wherein the opening segments both the first and second conductive layers into at least four control gate electrodes positioned laterally adjacent the opening.
Claim 18
Dependent Claim
20 words
The transistor of claim 11 wherein a gate dielectric layer is formed between the floating gate and the channel region.
Claim 19
Dependent Claim
24 words
The transistor of claim 11 wherein a gate dielectric layer is formed between the floating gate and the at least two control gate electrodes.
Claim 20
Dependent Claim
45 words
The transistor of claim 11 wherein the sidewalls of the at least two control gate electrodes are substantially slanted or curved to increase a surface area of the sidewalls to improve capacitance between the at least two control gate electrodes and the floating gate electrode.
Claim 21
Dependent Claim
28 words
The transistor of claim 11 wherein each control gate electrode in the at least two control gate electrodes are independent electrodes isolated from one another by dielectric layers.
Claim 22
Dependent Claim
24 words
The transistor of claim 11 wherein the floating gate electrode is made of a silicon containing semiconductive material portion and a metallic material portion.
Claim 23
Dependent Claim
20 words
The transistor of claim 11 wherein the at least two control gate electrodes are made of polysilicon or amorphous silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |