Merged bipolar and CMOS circuit and method

Claim 1

A method for fabricating a BiCMOS integrated circuit, comprising the steps of: forming in a single implantation step a base region of a bipolar transistor and a p-well of an n-channel MOS transistor; and forming in a single implantation step a collector contact well of a bipolar transistor and an n-well of a p-channel MOS transistor, said collector contact well adjoining a collector region and extending to a surface of a semiconductor substrate.

Claim 2

A method for fabricating a BiCMOS integrated circuit, comprising the steps of: forming in a single implantation step a base region of a bipolar transistor and a p-well of an n-channel MOS transistor; and forming in a single implantation step a collector contact well of a bipolar transistor and an n-well of a p-channel MOS transistor, said collector contact well adjoining a collector region and extending to a surface of a semiconductor substrate.

Claim 3

A method for fabricating a BiCMOS integrated circuit, comprising the steps of: forming an n-type collector region within a semiconductor substrate of lighter doping; forming a plurality of p-type wells, at least one of said plurality of p-type wells forming a base region lying between said collector region and a surface of said semiconductor substrate, said base region adjoining said collector region and extending to said surface, and at least one of said plurality of p-type wells forming an n-channel MOS well; forming a plurality of n-type wells, at least one of said plurality of n-type wells forming a collector contact well lying between said collector region and said surface of said semiconductor substrate, said collector contact well adjoining said collector region and extending to said surface, further said collector contact well lying between said base region and said n-channel MOS well, and at least one of said plurality of n-type wells forming a p-channel MOS well; and forming an emitter region adjoining said base region, said emitter region extending to said surface.

Claim 4

A method for fabricating a BiCMOS integrated circuit, comprising the steps of: forming an n-type collector region within a semiconductor substrate of lighter doping; forming a plurality of p-type wells, at least one of said plurality of p-type wells forming a base region lying between said collector region and a surface of said semiconductor substrate, said base region adjoining said collector region and extending to said surface, and at least one of said plurality of p-type wells forming an n-channel MOS well; forming a plurality of n-type wells, at least one of said plurality of n-type wells forming a collector contact well lying between said collector region and said surface of said semiconductor substrate, said collector contact well adjoining said collector region and extending to said surface, further said collector contact well lying between said base region and said n-channel MOS well, and at least one of said plurality of n-type wells forming a p-channel MOS well; and forming an emitter region adjoining said base region, said emitter region extending to said surface.