US4994887A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage merged bipolar/CMOS technology
Assignee: Texas Instruments Inc
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Filing: 1987-11-13
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Granted: 1991-02-19
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Expires: 2007-11-13
Abstract
Abstract An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.
Inventors
- 👤 Louis N. Hutter
- 👤 Mark E. Gibson
- 👤 Jeffrey P. Smith
- 👤 Shiu-Hang Yan
- 👤 Arnold C. Conway
- 👤 John P. Erdeljac
- 👤 James D. Goon
- 👤 AnhKim Duong
- 👤 Mary A. Murphy
- 👤 Susan S. Kearney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:14
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D84/00; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
232 words
An integrated circuit having NMOS, PMOS, and NPN transistors comprising: a first P type layer; N+ buried regions formed insaid first P type layer corresponding with the PMOS transistors and the NPN transistors; a second P type layer overlying said first P type layer and housing the NMOS transistors; N well regions formed in said second P type layer each of said N well regions housing a PMOS transistor or a bipolar transistor; and P+ buried regions disposed between said first and second P type layers and beneath the NMOS transistors, and P+ buried regions being substantially smaller than said N+ buried regions and being isolated from said N+ buried regions thereby forming an integrated circuit in which PMOS transistors are in an N well, which N well is on an N+ region, and in which NMOS transistors are on P type layers, which P type layers are on a P+ region, and in which NPN transistors are in an N well, which N well is on an N+ region, and in which the P+ regions are isolated from the N+ regions, whereby the N+ regions provide a low resistance region for the PMOS and NPN transistors and the P+ region provides a low resistance region for the NMOS transistors, and the isolation of the P+ regions from the N+ regions avoids high capacitance due to proximity of N+ and P+ regions.
Claim 2
Dependent Claim
232 words
An integrated circuit having NMOS, PMOS, and NPN transistors comprising: a first P type layer; N+ buried regions formed insaid first P type layer corresponding with the PMOS transistors and the NPN transistors; a second P type layer overlying said first P type layer and housing the NMOS transistors; N well regions formed in said second P type layer each of said N well regions housing a PMOS transistor or a bipolar transistor; and P+ buried regions disposed between said first and second P type layers and beneath the NMOS transistors, and P+ buried regions being substantially smaller than said N+ buried regions and being isolated from said N+ buried regions thereby forming an integrated circuit in which PMOS transistors are in an N well, which N well is on an N+ region, and in which NMOS transistors are on P type layers, which P type layers are on a P+ region, and in which NPN transistors are in an N well, which N well is on an N+ region, and in which the P+ regions are isolated from the N+ regions, whereby the N+ regions provide a low resistance region for the PMOS and NPN transistors and the P+ region provides a low resistance region for the NMOS transistors, and the isolation of the P+ regions from the N+ regions avoids high capacitance due to proximity of N+ and P+ regions.
Claim 3
Dependent Claim
28 words
The integrated circuit of claim 1, wherein said first P type layer is a first epitaxial layer, and said second P type layer is a second epitaxial layer.
Claim 4
Dependent Claim
161 words
An integrated circuit having NMOS, PMOS, and bipolar transistors, comprising: a P+ layer of semiconductor material; a first P layer of semiconductor material on a surface of said P+ layer; a second P layer of semiconductor material on said first P layer and having an interface with said first P layer, and separated from said P+ layer by said first P layer; N+ regions at the interface of said first and second P layers and spaced from said P+ layer; first and second N regions in said second P layer, each of said N regions adjacent a corresponding one of said N+ regions; N source and drain regions in said second P layer for an NMOS transistor; P source and drain regions insaid first N region for a PMOS transistor; and a P base region in said second N region, and an N emitter region in said P base region for a bipolar transistor with said second N region as collector.
Claim 5
Dependent Claim
161 words
An integrated circuit having NMOS, PMOS, and bipolar transistors, comprising: a P+ layer of semiconductor material; a first P layer of semiconductor material on a surface of said P+ layer; a second P layer of semiconductor material on said first P layer and having an interface with said first P layer, and separated from said P+ layer by said first P layer; N+ regions at the interface of said first and second P layers and spaced from said P+ layer; first and second N regions in said second P layer, each of said N regions adjacent a corresponding one of said N+ regions; N source and drain regions in said second P layer for an NMOS transistor; P source and drain regions insaid first N region for a PMOS transistor; and a P base region in said second N region, and an N emitter region in said P base region for a bipolar transistor with said second N region as collector.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |