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US6313486B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Floating gate transistor having buried strained silicon germanium channel layer

Assignee: Liberty Patents LLC
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Filing: 2000-06-15
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Granted: 2001-11-06
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Expires: 2020-06-15
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Abstract

Abstract A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.

Inventors

  • 👤 David L. Kencke
  • 👤 Sanjay K. Banerjee

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 13:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 88 words
A field effect transistor comprising: a) a silicon substrate, b) a source region and a drain region formed in spaced surface regions of the substrate, c) a channel region between the source region and the drain region, the channel region including a Si x Ge 1−x alloy layer epitaxially grown on the silicon substrate and a silicon cap layer epitaxially grown on the alloy layer, d) a floating gate over and insulated from the channel region, and e) a control gate over and insulated from the floating gate.
Claim 2
Dependent Claim 88 words
A field effect transistor comprising: a) a silicon substrate, b) a source region and a drain region formed in spaced surface regions of the substrate, c) a channel region between the source region and the drain region, the channel region including a Si x Ge 1−x alloy layer epitaxially grown on the silicon substrate and a silicon cap layer epitaxially grown on the alloy layer, d) a floating gate over and insulated from the channel region, and e) a control gate over and insulated from the floating gate.
Claim 3
Dependent Claim 19 words
The field effect transistor as defined by claim 1 wherein the Si x Ge 1−x alloy layer is graded.
Claim 4
Dependent Claim 29 words
The field effect transistor as defined by claim 2 wherein the Si x Ge 1−x alloy layer is graded from 1−x=0 to a maximum value in the growth direction.
Claim 5
Dependent Claim 19 words
The field effect transistor as defined by claim 3 wherein the Si x Ge 1−x layer is compressively strained.
Claim 6
Dependent Claim 28 words
The field effect transistor as defined by claim 4 wherein the thickness of the Si x Ge 1−x layer is below a critical value to maintain pseudomorphic strain.
Claim 7
Dependent Claim 19 words
The field effect transistor as defined by claim 1 wherein the Si x Ge 1−x layer is compressively strained.
Claim 8
Dependent Claim 28 words
The field effect transistor as defined by claim 6 wherein the thickness of the Si x Ge 1−x layer is below a critical value to maintain pseudomorphic strain.
Claim 9
Dependent Claim 31 words
The field effect transistor as defined by claim 1 wherein the Si x Ge 1−x alloy layer and the silicon cap layer extend into the source region and the drain region.
Claim 10
Dependent Claim 18 words
The field effect transistor as defined by claim 8 wherein the silicon substrate has a monocrystalline lattice structure.
Claim 11
Dependent Claim 18 words
The field effect transistor as defined by claim 1 wherein the silicon substrate has a monocrystalline lattice structure.
Claim 12
Dependent Claim 90 words
A flash EEPROM device having improved electron injection for programming comprising a monocrystalline silicon body having spaced source and drain regions with a channel therebetween, the channel including a graded SiGe alloy layer epitaxially grown on the silicon body and a cap silicon layer epitaxially grown on the SiGe layer, and a gate structure overlying the channel region including a control gate and floating gate between the control gate and the channel region, the control gate and the floating gate being dielectrically isolated from each other and the semiconductor body.
Claim 13
Dependent Claim 90 words
A flash EEPROM device having improved electron injection for programming comprising a monocrystalline silicon body having spaced source and drain regions with a channel therebetween, the channel including a graded SiGe alloy layer epitaxially grown on the silicon body and a cap silicon layer epitaxially grown on the SiGe layer, and a gate structure overlying the channel region including a control gate and floating gate between the control gate and the channel region, the control gate and the floating gate being dielectrically isolated from each other and the semiconductor body.
Claim 14
Dependent Claim 17 words
The flash EEPROM device as defined by claim 11 wherein the SiGe alloy layer is compressively strained.
Claim 15
Dependent Claim 29 words
The flash EEPROM device as defined by claim 12 wherein the alloy layer is Si x Ge 1−x and is graded from 1−x=0 to 1−x being a maximum value.
Claim 16
Dependent Claim 23 words
The flash EEPROM device as defined by claim 13 wherein the SiGe layer and the cap layer extend into the source and drain.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-11-05 2005-05-07 2005-11-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-11-05 2009-05-07 2009-11-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-11-05 2013-05-07 2013-11-06 $7700.00 Window Closed / Lapsed

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