Abstract A method for fabricating an improved metal-insulator-metal or metal-insulator-polysilicon capacitor having high capacitance density and low noise is achieved. An insulating layer is provided overlying a semiconductor substrate. A capacitor bottom plate electrode is formed overlying the insulating layer. A thin capacitor dielectric layer is deposited overlying the capacitor bottom plate electrode. An etch stop layer is deposited overlying the capacitor dielectric layer. A thick oxide layer is deposited overlying the etch stop layer. The oxide layer over the capacitor bottom plate electrode is etched away stopping at the etch stop layer whereby a recess is formed in the oxide layer overlying the bottom plate electrode wherein sidewalls of the oxide layer overlie the edges of the bottom plate electrode. A capacitor top plate electrode is formed within the recess whereby a guard ring is formed on the sidewalls of the oxide layer within the recess and wherein gaps are left between the capacitor top plate electrode and the guard ring. The top plate electrode is covered with a dielectric layer wherein the gaps are filled by the dielectric layer. A via opening is formed through the dielectric layer to the capacitor top plate electrode and filled with a patterned metal layer to complete formation of a capacitor in the fabrication of an integrated circuit device.
An integrated circuit device with capacitor comprising: an interconnection line overlying an insulating layer on a semiconductor substrate; a first dielectric layer overlying said interconnection line wherein said first dielectric layer comprises a capacitor dielectric layer overlying said interconnection line, an etch stop layer overlying said capacitor dielectric layer, and an oxide layer overlying said etch stop layer; a metal line contacting said interconnection line through an opening in said first dielectric layer; a capacitor overlying an insulating layer on a semiconductor substrate and adjacent to said interconnection line comprising: a capacitor bottom plate electrode overlying said insulating layer on said semiconductor substrate; said capacitor dielectric layer overlying said capacitor bottom plate electrode; said etch stop layer overlying said capacitor dielectric layer; a capacitor top plate electrode overlying said etch stop layer over said capacitor bottom plate electrode within a recess formed in said oxide layer; and a guard ring on the sidewalls of said oxide layer within said recess wherein gaps are left between said capacitor top plate electrode and said guard ring; and a second dielectric layer covering said metal line and said top plate electrode wherein said gaps are filled by said second dielectric layer.
Claim 2
Dependent Claim
198 words
An integrated circuit device with capacitor comprising: an interconnection line overlying an insulating layer on a semiconductor substrate; a first dielectric layer overlying said interconnection line wherein said first dielectric layer comprises a capacitor dielectric layer overlying said interconnection line, an etch stop layer overlying said capacitor dielectric layer, and an oxide layer overlying said etch stop layer; a metal line contacting said interconnection line through an opening in said first dielectric layer; a capacitor overlying an insulating layer on a semiconductor substrate and adjacent to said interconnection line comprising: a capacitor bottom plate electrode overlying said insulating layer on said semiconductor substrate; said capacitor dielectric layer overlying said capacitor bottom plate electrode; said etch stop layer overlying said capacitor dielectric layer; a capacitor top plate electrode overlying said etch stop layer over said capacitor bottom plate electrode within a recess formed in said oxide layer; and a guard ring on the sidewalls of said oxide layer within said recess wherein gaps are left between said capacitor top plate electrode and said guard ring; and a second dielectric layer covering said metal line and said top plate electrode wherein said gaps are filled by said second dielectric layer.
Claim 3
Dependent Claim
29 words
The device according to claim 1 wherein said semiconductor substrate includes semiconductor device structures such as gate electrodes and source and drain regions and multiple levels of metal interconnections.
Claim 4
Dependent Claim
18 words
The device according to claim 1 wherein said interconnection line and said capacitor bottom plate electrode comprise metal.
Claim 5
Dependent Claim
18 words
The device according to claim 1 wherein said interconnection line and said capacitor bottom plate electrode comprise polysilicon.
Claim 6
Dependent Claim
24 words
The device according to claim 1 wherein said capacitor dielectric layer comprises silicon oxide having a thickness of between about 350 and 500 Angstroms.
Claim 7
Dependent Claim
24 words
The device according to claim 1 wherein said etch stop layer comprises silicon nitride having a thickness of between about 180 and 200 Angstroms.
Claim 8
Dependent Claim
20 words
The device according to claim 1 wherein said oxide layer has a thickness of between about 3000 and 5000 Angstroms.
Claim 9
Dependent Claim
27 words
The device according to claim 1 further comprising a patterned metal layer filling a via opening through said second dielectric layer to said capacitor top plate electrode.