Method of making high precision w-polycide-to-poly capacitors in digital/analog process

Claim 1

A method for forming a capacitor on a silicon substrate, comprising the steps of: forming a first layer of doped polysilicon over said silicon substrate; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor; forming an oxide layer over said bottom plate; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen) at a flow rate of about 10,000 sccm, then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; and annealing said bottom plate.

Claim 2

A method for forming a capacitor on a silicon substrate, comprising the steps of: forming a first layer of doped polysilicon over said silicon substrate; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor; forming an oxide layer over said bottom plate; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen) at a flow rate of about 10,000 sccm, then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; and annealing said bottom plate.

Claim 8

A method of forming an integrated circuit, in and on a silicon substrate, which includes a capacitor and an FET (Field Effect Transistor) device with polycide gate, comprising the steps of: forming field oxide regions and a gate oxide layer in and over said silicon substrate; forming a first layer of doped polysilicon over said field oxide regions and said gate oxide layer; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor, and to form said polycide gate; forming an oxide layer over the resultant structure wherein the polycide bottom plate and polycide gate are formed; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen), at a flow rate of about 10,000 sccm then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of doped polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; annealing said bottom plate; and forming source and drain regions for said FET device in said substrate adjacent to said polycide gate.

Claim 9

A method of forming an integrated circuit, in and on a silicon substrate, which includes a capacitor and an FET (Field Effect Transistor) device with polycide gate, comprising the steps of: forming field oxide regions and a gate oxide layer in and over said silicon substrate; forming a first layer of doped polysilicon over said field oxide regions and said gate oxide layer; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor, and to form said polycide gate; forming an oxide layer over the resultant structure wherein the polycide bottom plate and polycide gate are formed; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen), at a flow rate of about 10,000 sccm then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of doped polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; annealing said bottom plate; and forming source and drain regions for said FET device in said substrate adjacent to said polycide gate.