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EP0183623A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Precision high-value MOS capacitors

Assignee: Fairchild Semiconductor Corp
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Filing: 1985-11-27
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Granted: —
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Expires: 2005-11-27
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Abstract

Abstract A method for producing an improved capacitor in MOS technology utilizing a thin layer oxide dielectric to improve the active/parasitic capacitance ratio while maintaining a high breakdown voltage and a low leakage current. A polycrystalline silicon layer is formed over a silicon dioxide field region on a wafer of semi-conductor silicon. Phosphorus ions are implanted in the polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV. The surface of the polycrystalline silicon layer is oxidized to form an interpoly oxide, utilizing an oxidation temperature which, for the implant dosage of phosphorus ions used, is sufficient to make the interpoly oxide layer approximately 770 Angstroms thick. The structure is then annealed at a temperature of approximately 1100°C in oxygen and HC1. A second polycrystalline silicon layer is formed over the interpoly oxide layer, and the process completed in the conventional manner.

Inventors

  • 👤 Surinder Krishna

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 16:47
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10P; H10P95/00

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 94 words
A method for forming a capacitor on an integrated circuit structure comprising : forming a first polycrystalline silicon layer; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV: oxidizing the surface of the polycrystalline silicon layer to form an interpoly oxide layer, the oxidation being at a temperature which, for the implant dosage of the n-conductivity type ions, will make the interpoly oxide layer between approximately 770 and 2000 Angstroms thick; and forming a second polycrystalline silicon layer over said interpoly oxide layer.
Claim 2
Independent Claim 94 words
A method for forming a capacitor on an integrated circuit structure comprising : forming a first polycrystalline silicon layer; implanting n-conductivity type ions into the first polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV: oxidizing the surface of the polycrystalline silicon layer to form an interpoly oxide layer, the oxidation being at a temperature which, for the implant dosage of the n-conductivity type ions, will make the interpoly oxide layer between approximately 770 and 2000 Angstroms thick; and forming a second polycrystalline silicon layer over said interpoly oxide layer.
Claim 3
Dependent Claim 27 words
The method of claim 1 wherein the oxidizing step comprises: annealing the interpoly oxide layer in a geaseous mixture including HC1 at a temperature of approximately 1100°C.
Claim 4
Dependent Claim 17 words
The method of claim 2 wherein the first polycrystalline silicon layer is formed over an insulating layer.
Claim 5
Dependent Claim 21 words
The method of claim 3 wherein the insulating layer comprises a field isolation region of silicon dioxide approximately 1400 Angstroms thick.
Claim 6
Independent Claim 21 words
The method of any one of claims 2 to 4 wherein the n-conductivity type ions comprise one of phosphorus or arsenic.
Claim 7
Independent Claim 24 words
The method of any one of claims 2 to 5 wherein the first polycrystalline silicon layer is formed at a temperature of approximately 600°C.
Claim 8
Independent Claim 224 words
The method of any one of claims 2 to 6 wherein said oxidizing step comprises: inserting the integrated circuit structure into a diffusion furnace containing N 2 and 0 2 at standard pressure and a flow rate of approximately 300 cubic centimeters per minute at approximately 850°C; increasing the temperature inside the diffusion furnace from approximately 850°C to approximately 1000°C at a rate of approximately 8°C per minute; replacing the N 2 and 0 2 with 0 2 at standard pressure and a flow rate of approximately 3000 cubic centimeters per minute for approximately 20 minutes; replacing the O 2 with a mixture of approximately 3% HC1 and 97% O 2 for approximately 21 minutes; replacing the O 2 and HC1 with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute; increasing the temperature inside the diffusion furnace to approximately 1100°C over approximately a 20 minute period; replacing the N 2 with a mixture of approximately 95.4% N 2 , 3.4% 0 2 and 1.2% HC1 for approximately 60 minutes; replacing the mixture with N 2 at standard pressure and a flow rate of approximately 5000 cubic centimeters per minute: decreasing the temperature inside the diffusion furnace to approximately 850°C over a period of approximately 60 minutes; and removing the integrated circuit structure from the diffusion furnace.
Claim 9
Dependent Claim 32 words
The method of claim 7 wherein said implanting step comprises implanting the n-conductivity type ions into the first polycrystalline silicon layer at an implant dosage of approximately 3 x 10 15 ions/cm2.

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