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US5554558A
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Method of making high precision w-polycide-to-poly capacitors in digital/analog process
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-02-13
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Granted: 1996-09-10
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Expires: 2015-02-13
Abstract
Abstract A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.
Inventors
- 👤 Shun-Liang Hsu
- 👤 Jyh-Kang Ting
- 👤 Chun-Yi Shih
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:55
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D84/00; H10D84/80; H10D84/811; H10D84/813; H10P; H10P95/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
181 words
A method for forming a capacitor on a silicon substrate, comprising the steps of: forming a first layer of doped polysilicon over said silicon substrate; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor; forming an oxide layer over said bottom plate; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen) at a flow rate of about 10,000 sccm, then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; and annealing said bottom plate.
Claim 2
Independent Claim
181 words
A method for forming a capacitor on a silicon substrate, comprising the steps of: forming a first layer of doped polysilicon over said silicon substrate; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor; forming an oxide layer over said bottom plate; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen) at a flow rate of about 10,000 sccm, then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; and annealing said bottom plate.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said oxide layer is deposited to a thickness of between about 300 and 500 Angstroms.
Claim 4
Dependent Claim
45 words
The method of claim 1 wherein said oxide layer is formed by high temperature oxidation using N 2 O and SiH 2 Cl 2 at a temperature of between about 750° and 850° C., resulting in a thickness of between about 300 and 500 Angstroms.
Claim 5
Dependent Claim
24 words
The method of claim 1 wherein said silicide layer is formed of WSi x (tungsten silicide), wherein x is between about 2.3 and 2.8.
Claim 6
Dependent Claim
40 words
The method of claim 1 wherein said silicide layer is formed to a thickness of between about 1000 and 2000 Angstroms, by depositing tungsten fluoride (WF 6 ) and silane (SiH 4 ) using LPCVD (Low Pressure Chemical Vapor Deposition).
Claim 7
Dependent Claim
22 words
The method of claim 1 wherein said polycide bottom plate is annealed at a temperature of between about 850° and 1000° C.
Claim 8
Independent Claim
253 words
A method of forming an integrated circuit, in and on a silicon substrate, which includes a capacitor and an FET (Field Effect Transistor) device with polycide gate, comprising the steps of: forming field oxide regions and a gate oxide layer in and over said silicon substrate; forming a first layer of doped polysilicon over said field oxide regions and said gate oxide layer; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor, and to form said polycide gate; forming an oxide layer over the resultant structure wherein the polycide bottom plate and polycide gate are formed; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen), at a flow rate of about 10,000 sccm then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of doped polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; annealing said bottom plate; and forming source and drain regions for said FET device in said substrate adjacent to said polycide gate.
Claim 9
Independent Claim
253 words
A method of forming an integrated circuit, in and on a silicon substrate, which includes a capacitor and an FET (Field Effect Transistor) device with polycide gate, comprising the steps of: forming field oxide regions and a gate oxide layer in and over said silicon substrate; forming a first layer of doped polysilicon over said field oxide regions and said gate oxide layer; forming a silicide layer over said first layer of doped polysilicon; patterning said first layer of doped polysilicon and said silicide layer to form a polycide bottom plate of said capacitor, and to form said polycide gate; forming an oxide layer over the resultant structure wherein the polycide bottom plate and polycide gate are formed; first heating said oxide layer to a temperature of about 800° C. for about 30 minutes in 100% N2 (nitrogen), at a flow rate of about 10,000 sccm then densifying said oxide layer at a temperature of between about 800° and 900° C. in an atmosphere of between about 5 and 10 percent oxygen (O2), said oxygen having a flow rate of between about 500 and 1000 sccm; forming a second layer of doped polysilicon over said oxide layer; patterning said second layer of doped polysilicon to form a top plate of said capacitor; removing said oxide layer except under said top plate of said capacitor, where it acts as a capacitor dielectric; annealing said bottom plate; and forming source and drain regions for said FET device in said substrate adjacent to said polycide gate.
Claim 10
Dependent Claim
21 words
The method of claim 7 wherein said oxide layer is deposited to a thickness of between about 300 and 500 Angstroms.
Claim 11
Dependent Claim
45 words
The method of claim 7 wherein said oxide layer is formed by high temperature oxidation using N 2 O and SiH 2 Cl 2 at a temperature of between about 750° and 850° C., resulting in a thickness of between about 300 and 500 Angstroms.
Claim 12
Dependent Claim
24 words
The method of claim 7 wherein said silicide layer is formed of WSi x (tungsten silicide), wherein x is between about 2.3 and 2.8.
Claim 13
Dependent Claim
35 words
The method of claim 7 wherein said silicide layer is formed to a thickness of between about 1000 and 2000 Angstroms, by depositing tungsten fluoride (WF 6 ) and silane (SiH 4 ) using LPCVD.
Claim 14
Dependent Claim
22 words
The method of claim 7 wherein said polycide bottom plate is annealed at a temperature of between about 850° and 1000° C.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-10 | 2000-03-11 | 2000-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-10 | 2004-03-11 | 2004-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-10 | 2008-03-11 | 2008-09-10 | $7700.00 | Window Closed / Lapsed |