US5268315A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Implant-free heterojunction bioplar transistor integrated circuit process
Assignee: Maxim Integrated Products Inc
•
Filing: 1992-09-04
•
Granted: 1993-12-07
•
Expires: 2012-09-04
Abstract
Abstract The disclosed HBT IC process can fabricate npn heterojunction bipolar transistors, Schottky diodes, MIM capacitors, spiral inductors, and NiCr resistors. Two levels of interconnect metal are available. The first level metal is a conventional dielectric-insulated metal conductor. The second level metal includes an air-bridge for contacting the HBT emitters, which are on top of three level mesa structures. It is also an advanced low loss, low capacitance, air dielectric conductor useful for long interconnects and inductors. MIM capacitors are formed by sandwiching silicon nitride between the first layer metal and a capacitor top plate made with landed air-bridge metal. Precision thin film resistors are fabricated by depositing NiCr on silicon nitride. The three-level active mesa structure is etched down to the GaAs substrate, for lateral device isolation, with a truncated pyramidal shape which permits good step coverage of dielectric and metallization layers. The wet etching process uses a composition of H3PO4:H2O2:H2O in a preferred ratio of about 3:1:25 for the AlGaAs/GaAs system.
Inventors
- 👤 Jayasimha S. Prasad
- 👤 Song W. Park
- 👤 William A. Vetanen
- 👤 Irene G. Beers
- 👤 Curtis M. Haynes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:21
CPC Classifications
H; H10; H10W; H10W10/00; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/05; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646; H10W10/01; H10W20/00; H10W20/40; H10W20/482; H10W20/483; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
215 words
A heterojunction bipolar transistor (HBT) integrated circuit fabrication process comprising: forming at least three heterojunction bipolar transistor (HBT) layers of predetermined thicknesses and conductivities on a semi-insulating substrate, including a first-grown collector layer contacting an upper surface of the semi-insulating substrate, a second-grown base layer atop the collector layer, and a third-grown emitter layer atop the base layer; masking, patterning and etching the third-grown layer to form a truncated pyramidal emitter mesa having a predetermined first width at a bottom surface, and thereby exposing the base layer around the emitter mesa; masking, patterning and etching the second- and first-grown layers to form a base mesa having a predetermined second width greater than the first width, and to form a truncated pyramidal collector mesa having a predetermined third width at a bottom surface greater than the second width; etching through the first-grown layer to expose the upper surface of the semi-insulating substrate all around the collector mesa, the base and emitter mesas being stacked on the collector mesa to form a bipolar transistor; depositing a passivating layer over the upper surface of the semi-insulating substrate and the mesas to isolate the bipolar transistor on the substrate; and forming emitter, base and collector contacts through the passivating layer to contact respectively the emitter, base and collector mesas.
Claim 2
Dependent Claim
215 words
A heterojunction bipolar transistor (HBT) integrated circuit fabrication process comprising: forming at least three heterojunction bipolar transistor (HBT) layers of predetermined thicknesses and conductivities on a semi-insulating substrate, including a first-grown collector layer contacting an upper surface of the semi-insulating substrate, a second-grown base layer atop the collector layer, and a third-grown emitter layer atop the base layer; masking, patterning and etching the third-grown layer to form a truncated pyramidal emitter mesa having a predetermined first width at a bottom surface, and thereby exposing the base layer around the emitter mesa; masking, patterning and etching the second- and first-grown layers to form a base mesa having a predetermined second width greater than the first width, and to form a truncated pyramidal collector mesa having a predetermined third width at a bottom surface greater than the second width; etching through the first-grown layer to expose the upper surface of the semi-insulating substrate all around the collector mesa, the base and emitter mesas being stacked on the collector mesa to form a bipolar transistor; depositing a passivating layer over the upper surface of the semi-insulating substrate and the mesas to isolate the bipolar transistor on the substrate; and forming emitter, base and collector contacts through the passivating layer to contact respectively the emitter, base and collector mesas.
Claim 3
Dependent Claim
37 words
An HBT fabrication process according to claim 1 including determining a current gain of the HBT layers after forming the collector mesa and prior to depositing the passivating layer and forming the emitter, base and collector contacts.
Claim 4
Dependent Claim
167 words
An HBT fabrication process according to claim 1, wherein the steps of masking, patterning and etching the second- and first-grown layers, of etching through the first-grown layer, of depositing a passivating layer, and of forming contacts include: masking, patterning and etching the second- and first-gown layers at a location spaced laterally from the collector mesa to form a cathode mesa having a predetermined width etching through the first-grown layer to form a subcathode mesa having a predetermined width greater than the cathode mesa width and to expose the upper surface of the semi-insulating substrate all around the subcathode mesa, the cathode mesa being stacked on the subcathode mesa to form a Schottky diode; depositing the passivating layer over the upper surface of the semi-insulating substrate and the cathode and subcathode mesas to isolate the cathode and subcathode mesas from the bipolar transistor on the substrate; and forming anode and cathode contacts through the passivating layer to contact respectively the upper surfaces of the cathode and subcathode mesas.
Claim 5
Dependent Claim
61 words
An HBT fabrication process according to claim 3 including: forming the collector layer as two sublayers of differing doping concentrations so that the subcathode mesa has a greater doping concentration than the cathode mesa; and etching a gate recess in the cathode mesa through the base layer to reduce the thickness of the cathode mesa sublayer prior to forming the anode.
Claim 6
Dependent Claim
24 words
An HBT fabrication process according to claim 4 in which the reduced thickness of the cathode mesa is in a range of 1500-1800 Å.
Claim 7
Dependent Claim
44 words
An HBT fabrication process according to claim 1 including: forming a resistive metal layer on the passivation layer; forming resistor contacts at locations spaced apart across the resistive metal layer; and forming a second passivation layer over the resistor contacts and resistive metal layer.
Claim 8
Dependent Claim
92 words
An HBT fabrication process according to claim 1 including: depositing and patterning a first level metal layer in contact with selected ones of the emitter, base and collector contacts to form a first interconnection of the transistor to other devices formed on the substrate; forming a third passivation layer over the patterned first level metal layer; and depositing and patterning a second level metal layer in contact with selected portions of the patterned first level metal layer to form a second interconnection of the transistor to other devices formed on the substrate.
Claim 9
Dependent Claim
79 words
An HBT fabrication process according to claim 7 wherein a capacitor is formed in parallel with forming the first and second level metal layers, including: forming a portion of the first level metal layer as a first capacitor plate on the passivating layer; depositing a third passivation layer over the first level metal layer; and forming a portion of the second level metal layer as a second capacitor plate on the third passivation layer over the first capacitor plate.
Claim 10
Dependent Claim
59 words
An HBT fabrication process according to claim 8 wherein an inductor is formed integrally with the capacitor and transistor, including: forming an air bridge in the second level metal layer; connecting a first end of the air bridge to a selected contact of the transistor; and connecting a second end of the air bridge to the second capacitor plate.
Claim 11
Dependent Claim
64 words
An HBT fabrication process according to claim 1 in which the etching steps include wet etching the HBT layers with an etching composition comprising H 3 PO 4 :H 2 O 2 :H 2 O in a ratio of H 3 PO 4 :H 2 O 2 that is 2:1 or greater so that the HBT mesas are formed with a truncated pyramidal profile.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |