Method of integrating heterojunction bipolar transistors with heterojunction FETs and PIN diodes

Abstract

Abstract Generally, and in one form of the invention, a semi-insulating semiconductor substrate 10 is provided having a first surface. An HBT subcollector region 12 of a first conductivity type is implanted in the substrate 10 at the first surface. Next, an i-layer 16 is grown over the first surface, over which an HFET electron donor layer 18 of the first conductivity type is grown, the electron donor layer 18 having a wider energy bandgap than the i-layer. Subsequently, an HFET contact layer 20 of the first conductivity type is grown over the HFET donor layer 18. Next, the HFET contact 20 and donor 18 layers are etched away over the HBT subcollector region 12, after which an HBT base layer 22 of a second conductivity type is selectively grown on the i-layer 16 over the HBT subcollector region 12. Then, an HBT emitter layer 24/26/28 of the first conductivity type is selectively grown over the HBT base layer 22, the HBT emitter layer 24/26/28 having a wider energy bandgap than the HBT base layer 22. Afterwards, an isolation region 30 is implanted at the boundaries between the HFET contact layer 20 and the HBT emitter layer 24/26/28, the isolation region 30 extending down into the substrate 10. Next, a portion of the HFET contact layer 20 is etched away to form an HFET gate contact recess. Lastly, conductive contacts 34, 44, 32, 36 and 40 are formed to the HFET contact layer 20, the HFET gate contact recess, the HBT emitter layer 24/26/28, the HBT base layer 22 and the HBT subcollector region 12. Other devices, systems and methods are also disclosed.

Inventors

• 👤 Burhan Bayraktaroglu

Bibliographic Details