US4983532A
Expired / Lapsed
US
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Process for fabricating heterojunction bipolar transistors
Assignee: Hitachi Ltd
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Filing: 1988-12-20
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Granted: 1991-01-08
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Expires: 2008-12-20
Abstract
Abstract Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.
Inventors
- 👤 Katsuhiko Mitani
- 👤 Tomonori Tanoue
- 👤 Chushirou Kusano
- 👤 Susumu Takahashi
- 👤 Masayoshi Saito
- 👤 Hiroshi Miyazaki
- 👤 Fumio Murai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:30
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011; Y10S148/072; Y10S148/10
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
149 words
A process for fabricating a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein said subcollector layer is a heavily doped InGaAs layer; a step of establishing base contact through ion implantation; a step of forming a dielectric material in a collector electrode drawing-out region; a step of forming a dielectric layer on the surface of said epitaxial surface; and a step of etching part of said dielectric layer and said dielectric material formed in said collector electrode drawing-out region to form a hole reaching the surface of said subcollector and burying a metal serving as a collector electrode in said hole according to the selective CVD method.
Claim 2
Dependent Claim
149 words
A process for fabricating a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein said subcollector layer is a heavily doped InGaAs layer; a step of establishing base contact through ion implantation; a step of forming a dielectric material in a collector electrode drawing-out region; a step of forming a dielectric layer on the surface of said epitaxial surface; and a step of etching part of said dielectric layer and said dielectric material formed in said collector electrode drawing-out region to form a hole reaching the surface of said subcollector and burying a metal serving as a collector electrode in said hole according to the selective CVD method.
Claim 3
Dependent Claim
30 words
A process for fabricating a heterojunction bipolar transistor according to claim 1, wherein a metal to be buried is at least one member selected from among tungsten, aluminum, and copper.
Claim 4
Dependent Claim
143 words
A process for preparing a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that least one of the emitter junction and collector junction is a heterojunction, wherein said subcollector layer comprises a heavily doped InGaAs layer; a step of forming an external base through ion implantation; a step of forming a dielectric layer on the surface of said epitaxial surface; a step of etching part of said dielectric layer and a collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a SiO 2 layer only on the side wall of said hole; and a step of burying a metal serving as a collector electrode according to the selective CVD method.
Claim 5
Dependent Claim
143 words
A process for preparing a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that least one of the emitter junction and collector junction is a heterojunction, wherein said subcollector layer comprises a heavily doped InGaAs layer; a step of forming an external base through ion implantation; a step of forming a dielectric layer on the surface of said epitaxial surface; a step of etching part of said dielectric layer and a collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a SiO 2 layer only on the side wall of said hole; and a step of burying a metal serving as a collector electrode according to the selective CVD method.
Claim 6
Dependent Claim
30 words
A process for fabricating a heterojunction bipolar transistor according to claim 3, wherein said metal serving as a collector electrode is a member selected from among tungsten, aluminum, and copper.
Claim 7
Dependent Claim
179 words
A process for fabricating a heterojunction bipolar transistor, comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction; a step of forming an external base through ion implantation; a step of forming a dielectric layer on the surface of the epitaxially grown semiconductor layers; a step of etching part of said dielectric layer and a collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a first electrode on the surface of said exposed subcollector by a lift-off method; a step of forming a side wall dielectric layer; and a step of burying a metal serving as a collector electrode in said hole according to the selective CVD method, wherein said first electrode comprises a layer of AuGe formed on the surface of said exposed subcollector and a layer of W formed on said layer of AuGe.
Claim 8
Dependent Claim
179 words
A process for fabricating a heterojunction bipolar transistor, comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction; a step of forming an external base through ion implantation; a step of forming a dielectric layer on the surface of the epitaxially grown semiconductor layers; a step of etching part of said dielectric layer and a collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a first electrode on the surface of said exposed subcollector by a lift-off method; a step of forming a side wall dielectric layer; and a step of burying a metal serving as a collector electrode in said hole according to the selective CVD method, wherein said first electrode comprises a layer of AuGe formed on the surface of said exposed subcollector and a layer of W formed on said layer of AuGe.
Claim 9
Dependent Claim
33 words
A process for fabricating a heterojunction bipolar transistor according to claim 5, wherein said side wall dielectric layer is made of a material selected from the group consisting of SiO 2 and SiN.
Claim 10
Dependent Claim
24 words
A process for fabricating a heterojunction bipolar transistor according to claim 6, wherein said side wall dielectric layer is made of SiO 2 .
Claim 11
Dependent Claim
22 words
A process for fabricating a heterojunction bipolar transistor according to claim 6, wherein said side wall dielectric layer is made of SiN.
Claim 12
Dependent Claim
205 words
A process for fabricating a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction; a step of forming an external base through ion implantation; a step of forming a dielectric material in a collector electrode drawing-out region; a step of forming a dielectric layer on the surface of the epitaxially grown semiconductor layers; a step of etching part of said dielectric layer and said dielectric material formed in said collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a first electrode on the surface of said exposed subcollector by a lift-off method; and a step of forming a side wall dielectric layer only in the peripheral portion of said first electrode formed within said hole and burying a metal serving as a collector electrode according to the selective CVD method, wherein said first electrode comprises a layer of AuGe formed on the surface of said exposed subcollector and a layer of W formed on said layer of AuGe.
Claim 13
Dependent Claim
205 words
A process for fabricating a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction; a step of forming an external base through ion implantation; a step of forming a dielectric material in a collector electrode drawing-out region; a step of forming a dielectric layer on the surface of the epitaxially grown semiconductor layers; a step of etching part of said dielectric layer and said dielectric material formed in said collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a first electrode on the surface of said exposed subcollector by a lift-off method; and a step of forming a side wall dielectric layer only in the peripheral portion of said first electrode formed within said hole and burying a metal serving as a collector electrode according to the selective CVD method, wherein said first electrode comprises a layer of AuGe formed on the surface of said exposed subcollector and a layer of W formed on said layer of AuGe.
Claim 14
Dependent Claim
33 words
A process for fabricating a heterojunction bipolar transistor according to claim 9, wherein said side wall dielectric layer is made of a material selected from the group consisting of SiO 2 and SiN.
Claim 15
Dependent Claim
24 words
A process for fabricating a heterojunction bipolar transistor according to claim 10, wherein said side wall dielectric layer is made of SiO 2 .
Claim 16
Dependent Claim
22 words
A process for fabricating a heterojunction bipolar transistor according to claim 10, wherein said side wall dielectric layer is made of SiN.
Claim 17
Dependent Claim
34 words
A process for fabricating a heterojunction bipolar transistor according to claim 9, wherein said step of forming a dielectric material comprises ion implanting H + and B + into said collector electrode drawing-out region.
Claim 18
Dependent Claim
145 words
A process for preparing a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that least one of the emitter junction and collector junction is a heterojunction, wherein said subcollector layer comprises a heavily doped InGaAs layer; a step of forming an external base through ion implantation; a step of forming a dielectric layer on the surface of said epitaxial surface; a step of etching part of said dielectric layer and a collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a dielectric side wall layer only on the side wall of said hole; and a step of burying a metal serving as a collector electrode according to the selective CVD method.
Claim 19
Dependent Claim
145 words
A process for preparing a heterojunction bipolar transistor comprising: a step of successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that least one of the emitter junction and collector junction is a heterojunction, wherein said subcollector layer comprises a heavily doped InGaAs layer; a step of forming an external base through ion implantation; a step of forming a dielectric layer on the surface of said epitaxial surface; a step of etching part of said dielectric layer and a collector electrode drawing-out region to form a hole reaching the surface of said subcollector and forming a dielectric side wall layer only on the side wall of said hole; and a step of burying a metal serving as a collector electrode according to the selective CVD method.
References Cited (Backward Citations)
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