US6288436B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mixed fuse technologies
Assignee: Qimonda AG
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Filing: 1999-07-27
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Granted: 2001-09-11
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Expires: 2019-07-27
Abstract
Abstract A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.
Inventors
- 👤 Chandrasekhar Narayan
- 👤 Kenneth Arndt
- 👤 Toshiaki Kirihata
- 👤 David Lachtrupp
- 👤 Axel Brintzinger
- 👤 Gabriel Daniel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:47
CPC Classifications
H; H10; H10D; H10D89/00; H10P; H10P74/00; H10P74/23; H10P74/232; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W20/494
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
44 words
A fuse arrangement on a semiconductor integrated circuit wafer or module comprising: at least one fuse of a first fuse type; and at least one fuse of a second fuse type, said fuses of said first and second types being unconnected from one another.
Claim 2
Dependent Claim
44 words
A fuse arrangement on a semiconductor integrated circuit wafer or module comprising: at least one fuse of a first fuse type; and at least one fuse of a second fuse type, said fuses of said first and second types being unconnected from one another.
Claim 3
Dependent Claim
53 words
The fuse arrangement as recited in claim 1 , wherein fuses of said first type individually repair defects on said wafer, and fuses of said second type individually repair defects on said module, said fuses of said first type repairing said defects without affecting said fuses of said second type, and vice versa.
Claim 4
Dependent Claim
41 words
The fuse arrangement as recited in claim 1 , wherein said at least one fuse of said first fuse type is a laser activated fuse and said at least one fuse of said second fuse type is an electrically activated fuse.
Claim 5
Dependent Claim
42 words
The fuse arrangement as recited in claim 3 , wherein said semiconductor integrated circuit wafer is provided with a plurality of wiring levels, said electrically activated fuses and said laser activated fuses being positioned on any of said plurality of wiring levels.
Claim 6
Dependent Claim
45 words
The fuse arrangement as recited in claim 4 , wherein the location of said electrically activated fuses is determined by the resistance associated with said wiring level and the location of said laser activated fuses is determined by the metal thickness of said wiring levels.
Claim 7
Dependent Claim
52 words
The fuse arrangement as recited in claim 1 , wherein said fuses of said first type are activated prior to mounting said semiconductor integrated circuit substrate on a second level package, whereas said fuses of said second type are activated after mounting said semiconductor integrated circuit substrate on a second level package.
Claim 8
Dependent Claim
35 words
The fuse arrangement as recited in claim 1 , wherein said fuse of said first type repairs defects of a first type and said fuse of said second type repairs defects of a second type.
Claim 9
Dependent Claim
38 words
The fuse arrangement as recited in claim 7 , wherein said defects of a first type comprise defects generated during fabrication of said wafer, and said defects of said second type are defects generated while stressing said module.
Claim 10
Dependent Claim
70 words
A fuse arrangement on a semiconductor integrated circuit chip, the chip having a plurality of wiring levels, the fuse arrangement comprising: fuses of a first type being positioned on a first number of said wiring levels; and fuses of a second type being positioned on a second number of said wiring levels, said fuses of said first type and said fuses from said second type being disconnected from one another.
Claim 11
Dependent Claim
70 words
A fuse arrangement on a semiconductor integrated circuit chip, the chip having a plurality of wiring levels, the fuse arrangement comprising: fuses of a first type being positioned on a first number of said wiring levels; and fuses of a second type being positioned on a second number of said wiring levels, said fuses of said first type and said fuses from said second type being disconnected from one another.
Claim 12
Dependent Claim
55 words
A fuse arrangement on a semiconductor integrated circuit wafer or module comprising: fuses of a first type for repairing a first type of defects; and fuses of a second type for repairing a second type of defects, said fuses of said first type and said fuses from said second type being disconnected from one another.
Claim 13
Dependent Claim
55 words
A fuse arrangement on a semiconductor integrated circuit wafer or module comprising: fuses of a first type for repairing a first type of defects; and fuses of a second type for repairing a second type of defects, said fuses of said first type and said fuses from said second type being disconnected from one another.
Claim 14
Dependent Claim
31 words
The fuse arrangement as recited in claim 10 , wherein said fuses of said first type are laser activated fuses and said fuses of said second type are electrically activated fuses.
Claim 15
Dependent Claim
27 words
The fuse arrangement as recited in claim 10 , wherein said first type of defects are wafer defects, and said second type of defects are module defects.
Claim 16
Dependent Claim
39 words
The fuse arrangement as recited in claim 10 , wherein said defects of said first type are defects requiring activating chip redundancy means, whereas said defects of said second type are single cell fails requiring activating module level redundancies.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-10 | 2005-03-12 | 2005-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-10 | 2009-03-12 | 2009-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-10 | 2013-03-12 | 2013-09-11 | $7700.00 | Window Closed / Lapsed |