Voltage boosting power supply circuit of memory integrated circuit and method for controlling charge amount of voltage boosting power supply

Claim 2

A voltage boosting power supply circuit of a memory integrated circuit comprising: a first power supplier; a first fuse connected at one end to the first power supplier; a second power supplier; a second fuse connected at one end to the second power supplier; a voltage boosting controller connected to other ends of the first and second fuses for generating first and second logic control signals responsive to first and second power signals received from the respective first and second fuses; a voltage boosting enabling circuit for receiving the first and second logic control signals from the voltage boosting controller and outputting third, fourth and fifth logic control signals responsive to the first and second logic control signals and a voltage boosting enable signal, wherein said first fuse is interposed between the first power supplier and the voltage boosting enabling circuit and the second fuse is interposed between the second power supplier and the voltage boosting enabling circuit wherein the first and second fuses, voltage boosting controller, and first and second power suppliers are connected in series; and a voltage booster for varying a supplied charge from the voltage boosting power supply circuit by an amount responsive to a logic level of the third and fifth control signals.

Claim 3

The voltage boosting power supply circuit of claim 1, wherein the voltage boosting enabling circuit includes means for outputting a low logic signal as the third logic control signal when the first fuse is uncut.

Claim 4

The voltage boosting power supply circuit of claim 1, wherein the voltage boosting enabling circuit includes means for outputting a low logic signal as the fifth logic control signal when the second fuse is cut.

Claim 5

The voltage boosting power supply circuit of claim 1, wherein the first power supplier is a PMOS transistor having a source connected to a power supply, a gate connected to a ground voltage, and a drain connected to the one end of the first fuse.

Claim 6

The voltage boosting power supply circuit of claim 1, wherein the second power supplier is a PMOS transistor having a source connected to a power supply, a gate where a ground voltage is applied, and a drain connected to one end of the second fuse.

Claim 7

The voltage boosting power supply circuit of claim 1, wherein the first fuse is a laser fuse capable of being cut by laser.

Claim 8

The voltage boosting power supply circuit of claim 1, wherein the second fuse is a laser fuse cut by laser.

Claim 9

The voltage boosting power supply circuit of claim 1, wherein the voltage boosting controller comprises: an inverter for inverting a voltage boosting control signal; a first NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to the other end of the first fuse, and a grounded source; a first latch unit connected to a drain of the first NMOS transistor, for inverting and latching a signal generated from the drain of the first NMOS transistor and outputting the latched signal as the first logic control signal; a second NMOS transistor having a gate connected to an output terminal of the inverter, a drain connected to the other end of the second fuse, and a grounded source; and a second latch unit connected to the drain of the second NMOS transistor, for inverting and latching the signal generated from the drain of the second NMOS transistor and generating the latched signal as the second logic control signal.

Claim 10

The voltage boosting power supply circuit of claim 8, wherein the first latch unit comprises: an inverter for inverting a signal generated from the drain of the first NMOS transistor; and an NMOS transistor having a drain connected to an input terminal of the inverter, a gate connected to an output terminal of the inverter, and a grounded source.

Claim 11

The voltage boosting power supply circuit of claim 8, wherein the second latch unit comprises: an inverter for inverting a signal generated from the drain of the second NMOS transistor; and an NMOS transistor having a drain connected to an input terminal of the inverter, a gate connected to the output terminal of the inverter, and a grounded source.

Claim 12

The voltage boosting power supply circuit of claim 1, wherein the voltage boosting enabling unit comprises: a first inverter for inverting the voltage boosting enable signal; a second inverter for inverting an output signal of the first inverter; an NAND gate for NAND-operating the first logic control signal by an output signal of the second inverter; a first inverter chain for buffering an output signal of the NAND gate and generating the third logic control signal; a second inverter chain for buffering the output signal of the second inverter and generating the fourth logic control signal; an NOR gate for NOR-operating the second control signal and an output signal of the first inverter; a third inverter chain for buffering an output signal of the NOR gate and generating the fifth logic control signal.

Claim 13

The voltage boosting power supply circuit of claim 11, wherein the first inverter chain includes an odd number of inverters connected in series.

Claim 14

The voltage boosting power supply circuit of claim 11, wherein the second and third inverter chains include an equal number of inverters connected in series.

Claim 15

The voltage boosting power supply circuit of claim 11, wherein the second and third inverter chains include an even number of inverters connected in series.

Claim 16

The voltage boosting power supply circuit of claim 1, wherein the voltage booster comprises: an NMOS transistor having a drain and a gate connected to a power supply; a first capacitor connected between the third control signal and the source of the NMOS transistor; a second capacitor connected between the fourth control signal and the source of the NMOS transistor; and a third capacitor connected between the fifth control signal and the source of the NMOS transistor, and wherein the voltage boosting power supply is generated from the source of the NMOS transistor.

Claim 17

The voltage boosting power supply circuit of claim 1, further comprising a transmitter connected to an output terminal of the voltage booster, for transmitting a voltage boosting power supply from the voltage boosting power supply circuit.

Claim 20

The method of claim 17, wherein the first and second fuses are cut using a laser.

Claim 21

The method of claim 17, wherein the supplied charge amount of the voltage boosting power supply from the voltage booster increases when a number of operating capacitors of the voltage booster is more than a predetermined number of capacitors, and the supplied charge amount thereof is reduced when the number of operating capacitors of the voltage booster is less than the predetermined number of capacitors.

Claim 22

A voltage boosting power supply circuit of a memory integrated circuit comprising: a first power supplier; a first fuse connected at one end to the first power supplier; a second power supplier; a second fuse connected at one end to the second power supplier; a voltage boosting controller connected to other ends of the first and second fuses for generating first and second logic control signals responsive to first and second power signals received from the respective first and second fuses; a voltage boosting enabling circuit for receiving the first and second logic control signals from the voltage boosting controller and outputting third, fourth and fifth logic control signals responsive to the first and second logic control signals and a voltage boosting enable signal; and a voltage booster for varying a supplied charge amount of the voltage boosting power supply circuit by an amount responsive to a logic level of the third and fifth control signals, wherein the voltage booster comprises: an NMOS transistor having a drain and a gate connected to a power supply; a first capacitor connected between the third control signal and the source of the NMOS transistor; a second capacitor connected between the fourth control signal and the source of the NMOS transistor; and a third capacitor connected between the fifth control signal and the source of the NMOS transistor, and wherein the voltage boosting power supply is generated from the source of the NMOS transistor.

Claim 23

A voltage boosting power supply circuit of a memory integrated circuit comprising: a first power supplier; a first fuse connected at one end to the first power supplier; a second power supplier; a second fuse connected at one end to the second power supplier; a voltage boosting controller connected to other ends of the first and second fuses for generating first and second logic control signals responsive to first and second power signals received from the respective first and second fuses; a voltage boosting enabling circuit for receiving the first and second logic control signals from the voltage boosting controller and outputting third, fourth and fifth logic control signals responsive to the first and second logic control signals and a voltage boosting enable signal; and a voltage booster for varying a supplied charge amount of the voltage boosting power supply circuit by an amount responsive to a logic level of the third and fifth control signals, wherein the voltage booster comprises: an NMOS transistor having a drain and a gate connected to a power supply; a first capacitor connected between the third control signal and the source of the NMOS transistor; a second capacitor connected between the fourth control signal and the source of the NMOS transistor; and a third capacitor connected between the fifth control signal and the source of the NMOS transistor, and wherein the voltage boosting power supply is generated from the source of the NMOS transistor.