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US6284633B1
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Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode
Assignee: NXP USA Inc
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Filing: 1997-11-24
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Granted: 2001-09-04
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Expires: 2017-11-24
Abstract
Abstract A tPEN layer ( 108 ) having a tensile stress is formed over a conductive gate stack ( 104-106 ) provided on a semiconductor substrate. Following the formation of the conductive gate stack ( 104-106 ), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer ( 110 ) is formed and patterned to form a gate ( 122, 124 ).
Inventors
- 👤 Rajan Nagabushnam
- 👤 Stanley M. Filipiak
- 👤 Bruce Boeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:18
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; C; C23; C23C; C23C16/00; C23C16/22; C23C16/30; C23C16/34; C23C16/345; H10D64/01306; H10D64/01308; H10D64/01312; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6927; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
129 words
A method of forming a semiconductor device, comprising the sequential steps of: forming a gate dielectric layer over a semiconductor substrate; forming a doped polysilicon layer over the gate dielectric layer; forming a metal-containing layer over the doped polysilicon layer; forming a plasma enhanced chemically vapor deposited nitride-containing capping layer at a temperature less than approximately 500° C. over the metal-containing layer, wherein the nitride containing capping layer has a deposited tensile stress greater than approximately 300 MPa, and wherein a combination of the gate dielectric layer, the doped polysilicon layer, the metal-containing layer, and the nitride-containing capping layer form a gate stack; annealing the gate stack; patterning a resist layer over the gate stack to define a gate pattern; and etching the gate stack to form a gate.
Claim 2
Independent Claim
129 words
A method of forming a semiconductor device, comprising the sequential steps of: forming a gate dielectric layer over a semiconductor substrate; forming a doped polysilicon layer over the gate dielectric layer; forming a metal-containing layer over the doped polysilicon layer; forming a plasma enhanced chemically vapor deposited nitride-containing capping layer at a temperature less than approximately 500° C. over the metal-containing layer, wherein the nitride containing capping layer has a deposited tensile stress greater than approximately 300 MPa, and wherein a combination of the gate dielectric layer, the doped polysilicon layer, the metal-containing layer, and the nitride-containing capping layer form a gate stack; annealing the gate stack; patterning a resist layer over the gate stack to define a gate pattern; and etching the gate stack to form a gate.
Claim 3
Dependent Claim
23 words
The method of claim 1 , wherein annealing the gate stack is carried out at a temperature of approximately 850 to 1000° C.
Claim 4
Dependent Claim
19 words
The method of claim 2 , wherein the nitride-containing capping layer is further characterized as a silicon nitride layer.
Claim 5
Dependent Claim
25 words
The method of claim 3 , wherein the silicon nitride capping layer has a tensile stress greater than 150 MPa after the step of annealing.
Claim 6
Dependent Claim
18 words
The method of claim 1 , wherein the deposited tensile stress is in a range of 300-1000 MPa.
Claim 7
Dependent Claim
56 words
The method of claim 1 , wherein forming a plasma enhanced chemically vapor deposited nitride-containing capping layer includes flowing a gaseous mixture into a plasma enhanced chemical vapor deposition reactor, wherein the gaseous mixture contains hydrogen, and the nitride-containing capping layer is formed having a hydrogen content within a range of 1 to 10 atomic %.
Claim 8
Dependent Claim
17 words
The method of claim 6 , wherein the gaseous mixture includes 3 to 8 atomic % hydrogen.
Claim 9
Dependent Claim
21 words
The method of claim 6 , wherein the gaseous mixture is subjected to an RF power of 150 to 500 Watts.
Claim 10
Dependent Claim
28 words
The method of claim 1 , further comprising forming source and drain regions in the semiconductor substrate, on opposing sides of the gate after annealing the gate stack.
Claim 11
Dependent Claim
19 words
The method of claim 1 , wherein the nitride-containing capping layer is further characterized as a silicon oxynitride layer.
Claim 12
Dependent Claim
18 words
The method of claim 1 , wherein the metal-containing layer is further characterized as a metal silicide layer.
Claim 13
Dependent Claim
19 words
The method of claim 11 , wherein the metal silicide layer is further characterized as a tungsten silicide layer.
Claim 14
Dependent Claim
42 words
The method of claim 12 , wherein annealing the gate stack changes a phase of the tungsten silicide layer from an amorphous phase to a tetragonal crystalline phase and no peeling of the nitride-containing capping layer occurs as a result of annealing.
Claim 15
Dependent Claim
18 words
The method of claim 1 , wherein the nitride-containing capping layer is further characterized as an antireflective layer.
Claim 16
Dependent Claim
22 words
The method of claim 14 , wherein the antireflective layer additionally prevents outgassing of dopants from the doped polysilicon layer during annealing.
Claim 17
Dependent Claim
39 words
The method of claim 15 , wherein the antireflective layer additionally acts as an etch stop layer in subsequent etch steps and insulates the gate stack from conductive layers that form contacts to active regions of the semiconductor substrate.
Claim 18
Dependent Claim
124 words
The method of claim 1 , wherein forming the nitride-containing capping layer having a deposited tensile stress greater than 300 MPa comprises: placing the semiconductor substrate into a plasma enhanced chemical vapor deposition chamber; and depositing the nitride containing capping layer using a deposition process having a processing temperature that is in a range of approximately 375-425° C., a process pressure that is in a range of approximately 4-5 Torr, an RF power that is in a range of approximately 250-350 Watts, a silane flow rate that is in a range of approximately 325-375 sccm, a NH 3 flow rate that is in a range of approximately 115-125 sccms, and an N 2 flow rate that is in a range of approximately 3100-3300 sccms.
Claim 19
Independent Claim
178 words
A method of forming a semiconductor device, comprising the sequential steps of: forming a gate dielectric layer over a semiconductor substrate; forming a doped polysilicon layer over the gate dielectric layer; forming a tungsten silicide layer over the polysilicon layer; forming a plasma enhanced chemically vapor deposited silicon nitride antireflective layer on the tungsten silicide layer at a temperature less than approximately 500° C., wherein the silicon nitride antireflective layer has a deposited tinsel stress greater than 300 megapascals; annealing the semiconductor substrate to change a phase of the tungsten silicide layer from an amorphous phase to a tetragonal crystalline phase, wherein the silicon nitride antireflective layer prevents outgassing of dopants from the polysilicon layer during annealing; patterning a resist layer on the silicon nitride antireflective layer to define exposed and unexposed regions; etching exposed regions defined by the photoresist layer to form a gate electrode from remaining portions of the tungsten silicide layer, the doped polysilicon layer, and the gate dielectric layer and an etch stop capping layer from remaining portions of the silicon nitride antireflective layer.
Claim 20
Independent Claim
178 words
A method of forming a semiconductor device, comprising the sequential steps of: forming a gate dielectric layer over a semiconductor substrate; forming a doped polysilicon layer over the gate dielectric layer; forming a tungsten silicide layer over the polysilicon layer; forming a plasma enhanced chemically vapor deposited silicon nitride antireflective layer on the tungsten silicide layer at a temperature less than approximately 500° C., wherein the silicon nitride antireflective layer has a deposited tinsel stress greater than 300 megapascals; annealing the semiconductor substrate to change a phase of the tungsten silicide layer from an amorphous phase to a tetragonal crystalline phase, wherein the silicon nitride antireflective layer prevents outgassing of dopants from the polysilicon layer during annealing; patterning a resist layer on the silicon nitride antireflective layer to define exposed and unexposed regions; etching exposed regions defined by the photoresist layer to form a gate electrode from remaining portions of the tungsten silicide layer, the doped polysilicon layer, and the gate dielectric layer and an etch stop capping layer from remaining portions of the silicon nitride antireflective layer.
Claim 21
Dependent Claim
39 words
The method of claim 18 , wherein annealing semiconductor substrate is carried out at a temperature of approximately 850 to 1000° C. and wherein a post anneal stress of the silicon nitride antireflective layer is greater than 150 MPa.
Claim 22
Dependent Claim
30 words
The method of claim 18 , wherein the deposited tensile stress of the silicon nitride antireflective layer prevents peeling of the silicon nitride antireflective layer during annealing the semiconductor substrate.
Claim 23
Dependent Claim
40 words
The method of claim 19 further comprising forming a conductive layer that forms a contact to an active region of the semiconductor substrate, wherein the etch stop capping layer insulates a portion of the gate electrode from the conductive layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-03 | 2005-03-05 | 2005-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-03 | 2009-03-05 | 2009-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-03 | 2013-03-05 | 2013-09-04 | $7700.00 | Window Closed / Lapsed |