Method for forming a T-gate for better salicidation

Claim 1

A method of forming a T-gate used with a salicide process for a semiconductor devices, comprising the steps of: a) patterning an insulating layer to form a dummy gate over a substrate; said substrate having a substrate surface; said insulation layer is patterned by forming a dummy gate resist pattern over said insulating layer using a first gate optical mask; said dummy gate resist pattern is exposed using said first optical mask, and etching said insulating layer using said dummy gate resist pattern as an etch mask; b) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask; c) forming a pad oxide layer over said substrate surface; d) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate; e) removing said dummy gate forming a gate opening exposing said substrate surface; f) forming a gate dielectric layer over said substrate surface in said gate opening; g) forming a gate layer over said dielectric layer and said substrate surface in said gate opening; h) patterning said gate layer to form a T-gate; said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer; said gate layer is patterned by using a T-gate resist pattern formed by using said first gate optical mask by over exposing a resist layer through said first optical gate mask so that the T-gate resist pattern is between 60% and 100% wider than said dummy gate resist; and i) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate.

Claim 2

A method of forming a T-gate used with a salicide process for a semiconductor devices, comprising the steps of: a) patterning an insulating layer to form a dummy gate over a substrate; said substrate having a substrate surface; said insulation layer is patterned by forming a dummy gate resist pattern over said insulating layer using a first gate optical mask; said dummy gate resist pattern is exposed using said first optical mask, and etching said insulating layer using said dummy gate resist pattern as an etch mask; b) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask; c) forming a pad oxide layer over said substrate surface; d) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate; e) removing said dummy gate forming a gate opening exposing said substrate surface; f) forming a gate dielectric layer over said substrate surface in said gate opening; g) forming a gate layer over said dielectric layer and said substrate surface in said gate opening; h) patterning said gate layer to form a T-gate; said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer; said gate layer is patterned by using a T-gate resist pattern formed by using said first gate optical mask by over exposing a resist layer through said first optical gate mask so that the T-gate resist pattern is between 60% and 100% wider than said dummy gate resist; and i) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate.

Claim 11

A method of forming a T-gate and using a salicide process; comprising the steps of: a) forming an insulating layer over a substrate; b) forming a dummy gate resist pattern over said insulating layer using a first gate optical mask; c) patterning said insulating layer to form a dummy gate over said substrate; said substrate having a substrate surface; d) removing said gate resist pattern; e) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask; f) forming a pad oxide layer over said substrate surface; g) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate; h) removing said dummy gate forming a gate opening exposing said substrate surface; i) forming a gate dielectric layer over said substrate surface in said gate opening; said gate opening having a width of between about 0.1 and 0.35 μm. j) forming a gate layer over said dielectric layer and said substrate surface in said gate opening; said gate layer is comprised of polysilicon; k) patterning said gate layer to form a T-gate by forming a T-gate resist pattern and etching said gate layer; said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer; said gate layer is pattern using a T-gate resist pattern that is formed by exposing a resist layer using said first gate optical mask; said T-gate resist pattern is between 60% and 100% wider than said dummy gate resist pattern and where said T-gate resist pattern is formed by overexposing a resist layer thorough said first gate optical mask; said T-gate has a gate top with a top width of between about 0.35 and 0.5 μm and a top height between 500 and 2000 Å; and a bottom width between 0.1 and 0.35 μm; and a bottom height between 1500 and 3500 Å; l) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate; m) forming source/drain (S/D) regions adjacent to said T-gate by an Ion implant process; n) forming a silicide layer over said T-gate and said substrate; to form silicide contacts to said source/drain (S/D) regions and gate contacts to the T-gate; o) forming a dielectric layer over the T-gate and substrate; p) forming contact opening through said dielectric layer to expose said source/drain regions and T-gate; and q) forming contacts to said source/drain regions and to said T-gate.

Claim 12

A method of forming a T-gate and using a salicide process; comprising the steps of: a) forming an insulating layer over a substrate; b) forming a dummy gate resist pattern over said insulating layer using a first gate optical mask; c) patterning said insulating layer to form a dummy gate over said substrate; said substrate having a substrate surface; d) removing said gate resist pattern; e) forming LDD regions adjacent to said dummy gate by ion implanting (I/I) impurity ions into said substrate using said dummy gate as a mask; f) forming a pad oxide layer over said substrate surface; g) forming a dielectric layer over said pad oxide layer and said dummy gate and removing said dielectric layer from over said dummy gate; h) removing said dummy gate forming a gate opening exposing said substrate surface; i) forming a gate dielectric layer over said substrate surface in said gate opening; said gate opening having a width of between about 0.1 and 0.35 μm. j) forming a gate layer over said dielectric layer and said substrate surface in said gate opening; said gate layer is comprised of polysilicon; k) patterning said gate layer to form a T-gate by forming a T-gate resist pattern and etching said gate layer; said T-gate filling said gate opening and extending laterally over a portion of said dielectric layer; said gate layer is pattern using a T-gate resist pattern that is formed by exposing a resist layer using said first gate optical mask; said T-gate resist pattern is between 60% and 100% wider than said dummy gate resist pattern and where said T-gate resist pattern is formed by overexposing a resist layer thorough said first gate optical mask; said T-gate has a gate top with a top width of between about 0.35 and 0.5 μm and a top height between 500 and 2000 Å; and a bottom width between 0.1 and 0.35 μm; and a bottom height between 1500 and 3500 Å; l) removing said dielectric layer and said pad oxide layer leaving said T-gate over said substrate; m) forming source/drain (S/D) regions adjacent to said T-gate by an Ion implant process; n) forming a silicide layer over said T-gate and said substrate; to form silicide contacts to said source/drain (S/D) regions and gate contacts to the T-gate; o) forming a dielectric layer over the T-gate and substrate; p) forming contact opening through said dielectric layer to expose said source/drain regions and T-gate; and q) forming contacts to said source/drain regions and to said T-gate.