US5998285A
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Self-aligned T-shaped process for deep submicron Si MOSFET's fabrication
Assignee: Winbond Electronics Corp
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Filing: 1998-07-30
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Granted: 1999-12-07
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Expires: 2018-07-30
Abstract
Abstract A process is disclosed for the fabrication of a MOS device with a T-shaped gate electrode, in which a selective CVD technique has been utilized to simplify the T-shaped gate process. After the formation of the gate oxide layer, no reactive ion etching step is applied, and that avoids the plasma charging damage to the gate oxide. The lightly-doped-drain structure and heavily-doped drain and source areas are formed in a self-aligned manner during the T-shaped gate process. The present invention provides a high yield rate and cost-saving in the T-shaped gate process for MOS devices.
Inventors
- 👤 Kuo-Yu Chou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:12
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/017; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
253 words
A method of forming a T-shaped gate structure in a MOS device, comprising the steps of: forming a dielectric layer on a 1st-type Si substrate, the dielectric layer defining a surface; applying a photolithographic and etching procedure over the dielectric layer to form a gate electrode pattern; injecting a 2nd-type ions into an area not masked by the dielectric layer by an ion implanting procedure; depositing a dielectric sacrificial layer such that a top surface of the dielectric sacrificial layer is higher than the surface of the dielectric layer; planarizing the top surface of the dielectric sacrificial layer such that the top surface of the dielectric layer is exposed; removing, by an etching technique, a portion of the dielectric layer enclosed by the dielectric sacrificial layer such that a surface of the 1st-type Si substrate is exposed; forming a gate oxide layer on the exposed surface of the 1st-type Si substrate; depositing a 1st polysilicon layer over the gate oxide layer such that a top surface of the 1st polysilicon layer is higher than the surface of the dielectric sacrificial layer; removing a portion of the 1st polysilicon layer which is above the surface of the dielectric sacrificial layer; depositing a 2nd polysilicon layer and thereby forming the T-shaped gate electrode over the 1st polysilicon layer by a selective chemical vapor deposition procedure; removing a portion of the dielectric sacrificial layer such that a thickness of a remaining portion of the dielectric sacrificial layer is larger than that of the gate oxide layer.
Claim 2
Independent Claim
253 words
A method of forming a T-shaped gate structure in a MOS device, comprising the steps of: forming a dielectric layer on a 1st-type Si substrate, the dielectric layer defining a surface; applying a photolithographic and etching procedure over the dielectric layer to form a gate electrode pattern; injecting a 2nd-type ions into an area not masked by the dielectric layer by an ion implanting procedure; depositing a dielectric sacrificial layer such that a top surface of the dielectric sacrificial layer is higher than the surface of the dielectric layer; planarizing the top surface of the dielectric sacrificial layer such that the top surface of the dielectric layer is exposed; removing, by an etching technique, a portion of the dielectric layer enclosed by the dielectric sacrificial layer such that a surface of the 1st-type Si substrate is exposed; forming a gate oxide layer on the exposed surface of the 1st-type Si substrate; depositing a 1st polysilicon layer over the gate oxide layer such that a top surface of the 1st polysilicon layer is higher than the surface of the dielectric sacrificial layer; removing a portion of the 1st polysilicon layer which is above the surface of the dielectric sacrificial layer; depositing a 2nd polysilicon layer and thereby forming the T-shaped gate electrode over the 1st polysilicon layer by a selective chemical vapor deposition procedure; removing a portion of the dielectric sacrificial layer such that a thickness of a remaining portion of the dielectric sacrificial layer is larger than that of the gate oxide layer.
Claim 3
Dependent Claim
30 words
A method according to claim 1, wherein the 1st-type Si substrate is a P-type Si substrate and the 2nd-type ion source of the ion implantation is a N-type ion source.
Claim 4
Dependent Claim
18 words
A method according to claim 1, wherein the dielectric sacrificial layer is a BPSG (Boron PhosphoSilicate Glass) layer.
Claim 5
Dependent Claim
32 words
A method according to claim 1, wherein the dielectric sacrificial layer is a two-layer structure, in which a bottom layer is a TEOS-oxide layer and an upper layer is a BPSG layer.
Claim 6
Dependent Claim
17 words
A method according to claim 1, wherein the planarization procedure is a CMP (Chemical Mechanical Polishing) technique.
Claim 7
Dependent Claim
17 words
A method according to claim 1, wherein the planarization procedure is a wet or dry etch-back process.
Claim 8
Dependent Claim
17 words
A method according to claim 1, wherein the etching procedure is a wet or dry etching process.
Claim 9
Dependent Claim
40 words
A method according to claim 1, wherein the dielectric sacrificial layer is a three-layer structure, in which a lowest layer is a TEOS-oxide layer, a middle layer is a BPSG layer, and a top layer is a dielectric sacrificial layer.
Claim 10
Dependent Claim
34 words
A method according to claim 1, wherein further comprises forming a heavily-doped drain area and a heavily-doped source area by a self-aligned N-type ion implanting process using the 2nd polysilicon layer as a mask.
Claim 11
Dependent Claim
36 words
A method according to claim 1, wherein the dielectric layer is formed by the following steps: depositing a pad oxide layer on the 1st-type Si substrate; depositing a silicon nitride layer on the pad oxide layer.
Claim 12
Dependent Claim
30 words
A method according to claim 1, wherein the 1st-type Si substrate is a N-type Si substrate and the 2nd-type ion source of the ion implantation is a P-type ion source.
Claim 13
Independent Claim
254 words
A method of forming a T-shaped gate structure in a MOS device, comprising the steps of: forming a dielectric layer on a 1st-type Si substrate, the dielectric layer defining a surface; defining an outline of a gate electrode over the dielectric layer and applying a etching procedure over the dielectric layer to form a gate electrode pattern; injecting a 2nd-type ions into an area not masked by the dielectric layer; forming a dielectric sacrificial layer such that a top surface of the dielectric sacrificial layer is higher than the surface of the dielectric layer; planarizing the top surface of the dielectric sacrificial layer such that the top surface of the dielectric layer is exposed; removing a portion of the dielectric layer enclosed by the dielectric sacrificial layer such that a surface of the 1st-type Si substrate is exposed; forming a gate oxide layer on the exposed surface of the 1st-type Si substrate; forming a 1st polysilicon layer over the gate oxide layer such that a top surface of the 1st polysilicon layer is higher than the surface of the dielectric sacrificial layer; removing a portion of the 1st polysilicon layer which is above the surface of the dielectric sacrificial layer; depositing a 2nd polysilicon layer and thereby forming the T-shaped gate electrode over the 1st polysilicon layer by a selective chemical vapor deposition procedure; removing a portion of the dielectric sacrificial layer such that a thickness of a remaining portion of the dielectric sacrificial layer is larger than that of the gate oxide layer.
Claim 14
Independent Claim
254 words
A method of forming a T-shaped gate structure in a MOS device, comprising the steps of: forming a dielectric layer on a 1st-type Si substrate, the dielectric layer defining a surface; defining an outline of a gate electrode over the dielectric layer and applying a etching procedure over the dielectric layer to form a gate electrode pattern; injecting a 2nd-type ions into an area not masked by the dielectric layer; forming a dielectric sacrificial layer such that a top surface of the dielectric sacrificial layer is higher than the surface of the dielectric layer; planarizing the top surface of the dielectric sacrificial layer such that the top surface of the dielectric layer is exposed; removing a portion of the dielectric layer enclosed by the dielectric sacrificial layer such that a surface of the 1st-type Si substrate is exposed; forming a gate oxide layer on the exposed surface of the 1st-type Si substrate; forming a 1st polysilicon layer over the gate oxide layer such that a top surface of the 1st polysilicon layer is higher than the surface of the dielectric sacrificial layer; removing a portion of the 1st polysilicon layer which is above the surface of the dielectric sacrificial layer; depositing a 2nd polysilicon layer and thereby forming the T-shaped gate electrode over the 1st polysilicon layer by a selective chemical vapor deposition procedure; removing a portion of the dielectric sacrificial layer such that a thickness of a remaining portion of the dielectric sacrificial layer is larger than that of the gate oxide layer.
Claim 15
Dependent Claim
21 words
A method according to claim 12, wherein the outline define step for the gate electrode is achieved by a photolithographic procedure.
Claim 16
Dependent Claim
18 words
A method according to claim 12, wherein the ion injection step is accomplished by an ion implanting process.
Claim 17
Dependent Claim
17 words
A method according to claim 12, wherein the dielectric sacrificial layer is formed by a deposition process.
Claim 18
Dependent Claim
20 words
A method according to claim 12, wherein the removal step of the dielectric layer is accomplished by an etching technique.
Claim 19
Dependent Claim
16 words
A method according to claim 12, wherein the gate oxide is formed by a growth process.
Claim 20
Dependent Claim
17 words
A method according to claim 12, wherein the 1st polysilicon layer is formed by a deposition process.
Claim 21
Dependent Claim
30 words
A method according to claim 12, wherein the 1st-type Si substrate is a P-type Si substrate and the 2nd-type ion source of the ion implantation is a N-type ion source.
Claim 22
Dependent Claim
18 words
A method according to claim 12, wherein the dielectric sacrificial layer is a BPSG (Boron PhosphoSilicate Glass) layer.
Claim 23
Dependent Claim
32 words
A method according to claim 12, wherein the dielectric sacrificial layer is a two-layer structure, in which a bottom layer is a TEOS-oxide layer and an upper layer is a BPSG layer.
Claim 24
Dependent Claim
17 words
A method according to claim 12, wherein the planarization procedure is a CMP (Chemical Mechanical Polishing) technique.
Claim 25
Dependent Claim
17 words
A method according to claim 12, wherein the planarization procedure is a wet or dry etch-back process.
Claim 26
Dependent Claim
16 words
A method according to claim 12, wherein the etching procedure a wet or dry etching process.
Claim 27
Dependent Claim
40 words
A method according to claim 12, wherein the dielectric sacrificial layer is a three-layer structure, in which a lowest layer is a TEOS-oxide layer, a middle layers is a BPSG layer, and a top layer is a dielectric sacrificial layer.
Claim 28
Dependent Claim
34 words
A method according to claim 12, wherein further comprises forming a heavily-doped drain area and a heavily-doped source area by a self-aligned N-type ion implanting process using the 2nd polysilicon layer as a mask.
Claim 29
Dependent Claim
36 words
A method according to claim 12, wherein the dielectric layer is formed by the following steps: depositing a pad oxide layer on the 1st-type Si substrate; depositing a silicon nitride layer on the pad oxide layer.
Claim 30
Dependent Claim
30 words
A method according to claim 12, wherein the 1st-type Si substrate is a N-type Si substrate and the 2nd-type ion source of the ion implantation is a P-type ion source.
Claim 31
Independent Claim
256 words
A method of forming a T-shaped gate structure in a MOS device, the method being characterized in that: forming a dielectric layer on a 1st-type Si substrate, the dielectric layer defining a surface; defining an outline of a gate electrode over the dielectric layer and applying an etching procedure over the dielectric layer to form a gate electrode pattern; injecting a 2nd-type ions into an area not masked by the dielectric layer; forming a dielectric sacrificial layer such that a top surface of the dielectric sacrificial layer is higher than the surface of the dielectric layer; planarizing the top surface of the dielectric sacrificial layer such that the top surface of the dielectric layer is exposed; removing a portion of the dielectric layer enclosed by the dielectric sacrificial layer such that a surface of the 1st-type Si substrate is exposed; forming a gate oxide layer on the exposed surface of the 1st-type Si substrate; forming a 1st polysilicon layer over the gate oxide layer such that a top surface of the 1st polysilicon layer is higher than the surface of the dielectric sacrificial layer; removing a portion of the 1st polysilicon layer which is above the surface of the dielectric sacrificial layer; depositing a 2nd polysilicon layer and thereby forming the T-shaped gate electrode over the 1st polysilicon layer by a selective chemical vapor deposition procedure; removing a portion of the dielectric sacrificial layer such that a thickness of a remaining portion of the dielectric sacrificial layer is larger than that of the gate oxide layer.
Claim 32
Independent Claim
256 words
A method of forming a T-shaped gate structure in a MOS device, the method being characterized in that: forming a dielectric layer on a 1st-type Si substrate, the dielectric layer defining a surface; defining an outline of a gate electrode over the dielectric layer and applying an etching procedure over the dielectric layer to form a gate electrode pattern; injecting a 2nd-type ions into an area not masked by the dielectric layer; forming a dielectric sacrificial layer such that a top surface of the dielectric sacrificial layer is higher than the surface of the dielectric layer; planarizing the top surface of the dielectric sacrificial layer such that the top surface of the dielectric layer is exposed; removing a portion of the dielectric layer enclosed by the dielectric sacrificial layer such that a surface of the 1st-type Si substrate is exposed; forming a gate oxide layer on the exposed surface of the 1st-type Si substrate; forming a 1st polysilicon layer over the gate oxide layer such that a top surface of the 1st polysilicon layer is higher than the surface of the dielectric sacrificial layer; removing a portion of the 1st polysilicon layer which is above the surface of the dielectric sacrificial layer; depositing a 2nd polysilicon layer and thereby forming the T-shaped gate electrode over the 1st polysilicon layer by a selective chemical vapor deposition procedure; removing a portion of the dielectric sacrificial layer such that a thickness of a remaining portion of the dielectric sacrificial layer is larger than that of the gate oxide layer.
Claim 33
Dependent Claim
30 words
A method according to claim 29, wherein the 1st-type Si substrate is a P-type Si substrate and the 2nd-type ion source of the ion implantation is a N-type ion source.
Claim 34
Dependent Claim
18 words
A method according to claim 29, wherein the dielectric sacrificial layer is a BPSG (Boron PhosphoSilicate Glass) layer.
Claim 35
Dependent Claim
32 words
A method according to claim 29, wherein the dielectric sacrificial layer is a two-layer structure, in which a bottom layer is a TEOS-oxide layer and an upper layer is a BPSG layer.
Claim 36
Dependent Claim
17 words
A method according to claim 29, wherein the planarization procedure is a CMP (Chemical Mechanical Polishing) technique.
Claim 37
Dependent Claim
17 words
A method according to claim 29, wherein the planarization procedure is a wet or dry etch-back process.
Claim 38
Dependent Claim
17 words
A method according to claim 29, wherein the etching step is a wet or dry etching process.
Claim 39
Dependent Claim
40 words
A method according to claim 29, wherein the dielectric sacrificial layer is a three-layer structure, in which a lowest layer is a TEOS-oxide layer, a middle layers is a BPSG layer, and a top layer is a dielectric sacrificial layer.
Claim 40
Dependent Claim
34 words
A method according to claim 29, wherein further comprises forming a heavily-doped drain area and a heavily-doped source area by a self-aligned N-type ion implanting process using the 2nd polysilicon layer as a mask.
Claim 41
Dependent Claim
36 words
A method according to claim 29, wherein the dielectric layer is formed by the following steps: depositing a pad oxide layer on the 1st-type Si substrate; depositing a silicon nitride layer on the pad oxide layer.
Claim 42
Dependent Claim
30 words
A method according to claim 29, wherein the 1st-type Si substrate is a N-type Si substrate and the 2nd-type ion source of the ion implantation is a P-type ion source.
References Cited (Backward Citations)
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