US5891783A
Expired / Lapsed
US
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Method of reducing fringe capacitance
Assignee: United Microelectronics Corp
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Filing: 1997-09-11
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Granted: 1999-04-06
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Expires: 2017-09-11
Abstract
Abstract A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed. A undoped silicate glass layer and a borophosphosilicate layer are formed in sequence, and an air gap is formed between the suspended part of the poly-gate and the substrate.
Inventors
- 👤 Chih-Hung Lin
- 👤 Jih-Wen Chou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/671; H10D64/675; H10D64/679
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
240 words
A method of reducing the fringe capacitance, comprising: providing a substrate doped with a first conductivity type of dopant, on which a buffer oxide layer is formed; forming a silicon nitride layer over the substrate; patterning the silicon nitride layer, using photolithography and etching processes, to form an opening and expose a portion of the buffer oxide layer; removing the exposed portion of the buffer oxide layer within the opening; lightly implanting the first conductivity type of dopant into the opening to simultaneously adjust a threshold voltage; forming a polysilicon layer over the substrate; patterning the polysilicon layer, using photolithography, to form a polysilicon gate covering the opening, the polysilicon gate having a width wider than the opening, so that two ends of the polysilicon gate cover a portion of the silicon nitride layer; etching away the silicon nitride layer and leaving the two ends of the polysilicon gate suspended in air over the substrate; lightly implanting, at a first angle, a second conductivity type of dopant into the substrate under the two suspended ends of the polysilicon gate; heavily implanting, at a second angle, the second conductivity type of dopant into the substrate beside the polysilicon gate to form a source/drain; forming an undoped silicate glass layer over the polysilicon gate, while maintaining an air gap between the two suspended ends of the polysilicon gate and the substrate; and forming a borophosphosilicate glass layer over the silicate glass layer.
Claim 2
Independent Claim
240 words
A method of reducing the fringe capacitance, comprising: providing a substrate doped with a first conductivity type of dopant, on which a buffer oxide layer is formed; forming a silicon nitride layer over the substrate; patterning the silicon nitride layer, using photolithography and etching processes, to form an opening and expose a portion of the buffer oxide layer; removing the exposed portion of the buffer oxide layer within the opening; lightly implanting the first conductivity type of dopant into the opening to simultaneously adjust a threshold voltage; forming a polysilicon layer over the substrate; patterning the polysilicon layer, using photolithography, to form a polysilicon gate covering the opening, the polysilicon gate having a width wider than the opening, so that two ends of the polysilicon gate cover a portion of the silicon nitride layer; etching away the silicon nitride layer and leaving the two ends of the polysilicon gate suspended in air over the substrate; lightly implanting, at a first angle, a second conductivity type of dopant into the substrate under the two suspended ends of the polysilicon gate; heavily implanting, at a second angle, the second conductivity type of dopant into the substrate beside the polysilicon gate to form a source/drain; forming an undoped silicate glass layer over the polysilicon gate, while maintaining an air gap between the two suspended ends of the polysilicon gate and the substrate; and forming a borophosphosilicate glass layer over the silicate glass layer.
Claim 3
Dependent Claim
17 words
The method according to claim 1, wherein the first conductivity type of dopant is a P-type dopant.
Claim 4
Dependent Claim
17 words
The method according to claim 2, wherein the second conductivity type of dopant is an N-type dopant.
Claim 5
Dependent Claim
17 words
The method according to claim 1, wherein the first conductivity type of dopant is a N-type dopant.
Claim 6
Dependent Claim
17 words
The method according to claim 4, wherein the second conductivity type of dopant is a P-type dopant.
Claim 7
Dependent Claim
30 words
The method according to claim 1, wherein said forming a silicon nitride layer includes forming the silicon nitride layer to a thickness of about 500 Å to about 2000 Å.
Claim 8
Dependent Claim
32 words
The method according to claim 6, wherein said forming an undoped silicate glass layer includes maintaining a thickness of the air gap in the range between about 500 Å and 2000 Å.
Claim 9
Dependent Claim
34 words
The method according to claim 7, further comprising forming a gate oxide layer having a thickness between about 50 Å to about 110 Å, within the opening and after said removing the exposed portion.
Claim 10
Dependent Claim
28 words
The method according to claim 1, wherein said forming a polysilicon layer includes forming the polysilicon layer to a thickness of about 500 Å to about 3000 Å.
Claim 11
Dependent Claim
36 words
The method according to claim 1, wherein said patterning the polysilicon layer includes forming the polysilicon gate to have a width that is about 0.05 μm to 0.1 μm wider than a width of the opening.
Claim 12
Dependent Claim
29 words
The method according to claim 10, wherein said forming an undoped silicate glass layer includes maintaining a width of the air gap to about 0.05 μm to 0.1 μm.
Claim 13
Dependent Claim
21 words
The method according to claim 1, wherein said lightly implanting includes implanting at a first angle of about 15° to 45°.
Claim 14
Dependent Claim
20 words
The method according to claim 1, wherein said heavily implanting includes implanting at second angle of about 0° to 7°.
Claim 15
Independent Claim
148 words
A method of reducing the fringe capacitance between a gate and a substrate comprising: forming a polysilicon gate covering an opening in a second dielectric layer formed over a first dielectric layer and the substrate, the polysilicon gate having a width wider than the opening, so that two ends of the polysilicon gate cover a portion of the second dielectric layer; removing the second dielectric layer so that the two ends of the polysilicon gate are suspended in air over the substrate; implanting a dopant into the substrate under the two suspended ends of the polysilicon gate; implanting a dopant into the substrate beside the polysilicon gate to form a source/drain; and forming an undoped layer over the polysilicon gate and contacting the first dielectric on opposing sides of the gate, while maintaining an air gap between the two suspended ends of the polysilicon gate and the substrate.
Claim 16
Independent Claim
148 words
A method of reducing the fringe capacitance between a gate and a substrate comprising: forming a polysilicon gate covering an opening in a second dielectric layer formed over a first dielectric layer and the substrate, the polysilicon gate having a width wider than the opening, so that two ends of the polysilicon gate cover a portion of the second dielectric layer; removing the second dielectric layer so that the two ends of the polysilicon gate are suspended in air over the substrate; implanting a dopant into the substrate under the two suspended ends of the polysilicon gate; implanting a dopant into the substrate beside the polysilicon gate to form a source/drain; and forming an undoped layer over the polysilicon gate and contacting the first dielectric on opposing sides of the gate, while maintaining an air gap between the two suspended ends of the polysilicon gate and the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |