US5448094A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Concave channel MOS transistor and method of fabricating the same
Assignee: United Microelectronics Corp
•
Filing: 1994-08-23
•
Granted: 1995-09-05
•
Expires: 2014-08-23
Abstract
Abstract A MOS transistor with concave channel and method of fabrication is provided. First, a LOCOS procedure is performed to form a field oxide layer on a silicon substrate by using a barrier layer as a mask. Next, the field oxide is removed to leave a concave area in the silicon substrate. Silicon dioxide sidewall spacers are formed apart on side walls of the barrier layer. A gate oxide layer is formed on the bottom of the concave area. A polysilicon layer is formed in conformity with the exposed surfaces of the barrier layer, the silicon dioxide sidewall spacers, and the gate oxide layer. A mask layer is formed overlying the polysilicon layer within the concave area. Then, portions of the polysilicon layer not covered by the mask layer are removed, so that the remained portion of the polysilicon layer and the gate oxide layer together construct a gate electrode, while the area under the gate electrode forms a concave channel. The mask layer and the barrier layer are removed respectively. Heavily doped source/drain areas are formed by a first ion implantation using the gate electrode and the silicon dioxide sidewall spacers as self-align masks. After removing the silicon dioxide sidewall spacers, lightly doped source/drain areas are formed by a second ion implantation using the gate electrode as a self-align mask.
Inventors
- 👤 Chen-Chung Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/608; H10D64/00; H10D64/01; H10D64/025
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
263 words
A method of fabricating a MOS transistor with a generally concave channel on a silicon substrate, comprising the steps of: forming a barrier layer overlying said silicon substrate, and patterning said barrier layer to expose a prospective gate electrode area of said silicon substrate; forming a field oxide layer on said prospective gate electrode area of said silicon substrate; removing said field oxide to leave a generally concave area in said silicon substrate; forming silicon dioxide sidewall spacers spaced apart at side walls of said barrier layer adjacent edges of said generally concave area; forming a gate oxide layer on a bottom of said generally concave area; forming a polysilicon layer conforming to exposed surfaces of said barrier layer, said silicon dioxide sidewall spacers, and said gate oxide layer; forming a mask layer overlying said polysilicon layer, and etching back to leave a portion of said mask layer within said concave area; removing portions of said polysilicon layer not covered by said mask layer, so that a remaining portion of said polysilicon layer and said gate oxide layer together define a gate electrode, wherein the area under said gate electrode forms a generally concave channel; removing said mask layer and said barrier layer; implanting first impurities into portions of said silicon substrate not covered by said gate electrode and said silicon dioxide sidewall spacers to form heavily doped source/drain areas; removing said silicon dioxide sidewall spacers; and implanting second impurities into portions of said silicon substrate not covered by said gate electrode to form lightly doped source/drain areas, thereby completing said MOS transistor.
Claim 2
Independent Claim
263 words
A method of fabricating a MOS transistor with a generally concave channel on a silicon substrate, comprising the steps of: forming a barrier layer overlying said silicon substrate, and patterning said barrier layer to expose a prospective gate electrode area of said silicon substrate; forming a field oxide layer on said prospective gate electrode area of said silicon substrate; removing said field oxide to leave a generally concave area in said silicon substrate; forming silicon dioxide sidewall spacers spaced apart at side walls of said barrier layer adjacent edges of said generally concave area; forming a gate oxide layer on a bottom of said generally concave area; forming a polysilicon layer conforming to exposed surfaces of said barrier layer, said silicon dioxide sidewall spacers, and said gate oxide layer; forming a mask layer overlying said polysilicon layer, and etching back to leave a portion of said mask layer within said concave area; removing portions of said polysilicon layer not covered by said mask layer, so that a remaining portion of said polysilicon layer and said gate oxide layer together define a gate electrode, wherein the area under said gate electrode forms a generally concave channel; removing said mask layer and said barrier layer; implanting first impurities into portions of said silicon substrate not covered by said gate electrode and said silicon dioxide sidewall spacers to form heavily doped source/drain areas; removing said silicon dioxide sidewall spacers; and implanting second impurities into portions of said silicon substrate not covered by said gate electrode to form lightly doped source/drain areas, thereby completing said MOS transistor.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein said barrier layer includes a pad oxide layer and a silicon nitride layer.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein said mask layer is a photoresist layer.
Claim 5
Dependent Claim
27 words
The method of claim 1, wherein said first impurities are arsenic ions with energy of about 80 KeV and dosage of about 5×10 15 atoms/cm 2 .
Claim 6
Dependent Claim
27 words
The method of claim 1, wherein said second impurities are phosphorous ions with energy of about 50 KeV and dosage of about 3×10 13 atoms/cm 2 .
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein the length of said concave channel is determined by the thickness and width of said field oxide.
Claim 8
Dependent Claim
177 words
A MOS transistor formed in a semiconductor substrate comprising: (a) a generally concave surface formed in said substrate; (b) a gate oxide layer covering a portion of said generally concave surface, said gate oxide layer having an essentially uniform thickness; (c) a conductive gate electrode disposed over said gate oxide layer, said conductive gate electrode having a central portion in contact with said gate oxide layer and having outwardly disposed wing-shaped portions which extend over and are spaced from portions of said generally concave surface by a distance which is greater than the thickness of said gate oxide layer; (d) first doped regions with a first concentration of an impurity therein defined in said semiconductor substrate outwardly of said generally concave surface, said first doped regions defining source/drain areas of said MOS transistor; and (e) second doped regions with a second concentration of an impurity therein defined in said semiconductor substrate between said first doped regions and points where said conductive gate electrode contacts said gate oxide layer, said second concentration being less than said first concentration.
Claim 9
Dependent Claim
177 words
A MOS transistor formed in a semiconductor substrate comprising: (a) a generally concave surface formed in said substrate; (b) a gate oxide layer covering a portion of said generally concave surface, said gate oxide layer having an essentially uniform thickness; (c) a conductive gate electrode disposed over said gate oxide layer, said conductive gate electrode having a central portion in contact with said gate oxide layer and having outwardly disposed wing-shaped portions which extend over and are spaced from portions of said generally concave surface by a distance which is greater than the thickness of said gate oxide layer; (d) first doped regions with a first concentration of an impurity therein defined in said semiconductor substrate outwardly of said generally concave surface, said first doped regions defining source/drain areas of said MOS transistor; and (e) second doped regions with a second concentration of an impurity therein defined in said semiconductor substrate between said first doped regions and points where said conductive gate electrode contacts said gate oxide layer, said second concentration being less than said first concentration.
Claim 10
Dependent Claim
19 words
The MOS transistor of claim 7 where said wing-shaped portions overhang and are spaced from said second doped regions.
Claim 11
Dependent Claim
12 words
The MOS transistor of claim 7 wherein said gate electrode comprises polysilicon.
Claim 12
Dependent Claim
33 words
The MOS Transistor of claim 7 wherein said second dope regions have an impurity profile which decreases in a direction towards said points where said conductive gate electrode contacts said gate oxide layer.
References Cited (Backward Citations)
US5105242A
Cited
US5142640A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |