US6274483B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to improve metal line adhesion by trench corner shape modification
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2000-01-18
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Granted: 2001-08-14
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Expires: 2020-01-18
Abstract
Abstract A new method is provided for the creation of the trenches or line patterns of damascene structures. Under the first embodiment of the invention, the trenches that are created for the copper interconnect lines are sputter etched as a result of which the corners of the trenches around the top elevation of the trenches are rounded. Under the second embodiment of the invention a disposable hard mask is created over the surface of the dielectric after which the trenches for the interconnect lines are created. The surface of the hard mask layer including the created trenches are rf sputter etched resulting in a sharp reduction of the angle of incidence between sidewalls of the trenches around the perimeter of the trenches and the surface of the layer of dielectric. The barrier and seed layers are deposited over the surface of the disposable hard mask including the created trenches, the deposited copper is polished down to the surface of the dielectric.
Inventors
- 👤 Weng Chang
- 👤 Ying-Ho Chen
- 👤 Syun-Ming Jang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/031; H10W20/056; H10W20/058
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
155 words
A method of creating interconnecting conductive lines and conductive vias in a layer of insulating material, comprising the steps of: providing a semiconductor substrate; depositing a layer of dielectric over a surface of said substrate; planarizing a surface of said layer of dielectric; creating trenches or openings in said layer of dielectric for deposition of metal thereby creating a pattern of interconnect lines or interconnect vias; sputter etching said created trenches or openings thereby faceting sidewalls of said trenches or openings by developing an ever-increasing facet or incline of sidewalls of said trenches or openings; depositing a barrier layer over a surface of said layer of dielectric thereby including inside surfaces of said trenches or openings; depositing a seed layer over a surface of said barrier layer; depositing a layer of copper over a surface of said seed layer; and polishing said layer of copper thereby forming a pattern of interconnect lines or interconnect vias.
Claim 2
Independent Claim
155 words
A method of creating interconnecting conductive lines and conductive vias in a layer of insulating material, comprising the steps of: providing a semiconductor substrate; depositing a layer of dielectric over a surface of said substrate; planarizing a surface of said layer of dielectric; creating trenches or openings in said layer of dielectric for deposition of metal thereby creating a pattern of interconnect lines or interconnect vias; sputter etching said created trenches or openings thereby faceting sidewalls of said trenches or openings by developing an ever-increasing facet or incline of sidewalls of said trenches or openings; depositing a barrier layer over a surface of said layer of dielectric thereby including inside surfaces of said trenches or openings; depositing a seed layer over a surface of said barrier layer; depositing a layer of copper over a surface of said seed layer; and polishing said layer of copper thereby forming a pattern of interconnect lines or interconnect vias.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said creating trenches or openings in said layer of dielectric is performed using reactive ion, plasma, sputter etch or RIE technologies.
Claim 4
Dependent Claim
72 words
The method of claim 1 wherein said depositing a barrier layer over a surface of said layer of dielectric is depositing a layer of material selected from a group containing titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN and Ti/W and is more preferably formed from TiN using rf sputtering of said barrier material whereby said barrier layer is preferably about 100 and 500 angstrom thick and more preferably about 300 angstrom thick.
Claim 5
Dependent Claim
92 words
The method of claim 1 wherein said depositing a seed layer over a surface of said barrier layer is using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr using copper or a copper alloy as a source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas whereby said seed layer is deposited to a minimum thickness of about 50 Angstrom.
Claim 6
Dependent Claim
74 words
The method of claim 1 with the additional step of depositing a hard mask layer over a surface of said layer of dielectric said step to be performed immediately prior to said step of creating trenches or openings in said layer of dielectric whereby said hard mask contains SiN or SiON or SiC and is sputter deposited over said planarized surface of said dielectric layer to a thickness between about 100 and 400 Angstrom.
Claim 7
Dependent Claim
37 words
The method of claim 1 wherein said polishing said layer of copper uses CMP techniques whereby said polishing of said layer of copper is continued to where a surface of said layer of dielectric is essentially reached.
Claim 8
Independent Claim
219 words
A method of creating interconnecting conductive lines and conductive vias in a layer of insulating material, comprising the steps of: providing a semiconductor substrate; depositing a layer of dielectric over a surface of said substrate; planarizing a surface of said layer of dielectric; depositing a sacrificial hard mask layer over a surface of said layer of dielectric; patterning and etching said hard mask layer thereby creating openings in said hard mask said openings to have a pattern that coincides with a pattern of said interconnecting conductive lines and conductive vias that are to be created in said layer of dielectric; creating trenches or openings in said layer of dielectric for deposition of metal thereby creating a pattern of interconnecting conductive lines and conductive vias; sputter etching said created trenches or openings thereby faceting sidewalls of said trenches or openings by developing an ever-increasing facet or incline of sidewalls of said trenches or openings; depositing a barrier layer over a surface of said hard mask layer thereby including inside surfaces of said pattern of interconnecting conductive lines and conductive vias; depositing a seed layer over a surface of said barrier layer; depositing a layer of copper over a surface of said seed layer; and polishing said layer of copper thereby forming a pattern of interconnecting conductive lines and conductive vias.
Claim 9
Independent Claim
219 words
A method of creating interconnecting conductive lines and conductive vias in a layer of insulating material, comprising the steps of: providing a semiconductor substrate; depositing a layer of dielectric over a surface of said substrate; planarizing a surface of said layer of dielectric; depositing a sacrificial hard mask layer over a surface of said layer of dielectric; patterning and etching said hard mask layer thereby creating openings in said hard mask said openings to have a pattern that coincides with a pattern of said interconnecting conductive lines and conductive vias that are to be created in said layer of dielectric; creating trenches or openings in said layer of dielectric for deposition of metal thereby creating a pattern of interconnecting conductive lines and conductive vias; sputter etching said created trenches or openings thereby faceting sidewalls of said trenches or openings by developing an ever-increasing facet or incline of sidewalls of said trenches or openings; depositing a barrier layer over a surface of said hard mask layer thereby including inside surfaces of said pattern of interconnecting conductive lines and conductive vias; depositing a seed layer over a surface of said barrier layer; depositing a layer of copper over a surface of said seed layer; and polishing said layer of copper thereby forming a pattern of interconnecting conductive lines and conductive vias.
Claim 10
Dependent Claim
57 words
The method of claim 7 wherein said depositing a sacrificial hard mask layer over a surface of said layer of dielectric is a sputter deposition process whereby said hard mask contains SiN or SiON or SiC and is sputter deposited over said planarized surface of said dielectric layer to a thickness between about 100 and 400 Angstrom.
Claim 11
Dependent Claim
97 words
The method of claim 7 wherein said patterning and etching said hard mask layer uses steps of photolithography whereby said hard mask layer is etched by applying an anisotropical etch using a solution of ammonium and hydrogen peroxide with an etch rate between about 300 and 900 Angstrom per minute thereby removing said hard mask in a pattern that is identical to a pattern of said interconnecting conductive lines and conductive vias whereby furthermore said removal of said hard mask simultaneously removes corners of said trenches or openings of said interconnecting conductive lines and said conductive vias.
Claim 12
Dependent Claim
27 words
The method of claim 7 wherein said creating trenches or openings in said layer of dielectric is performed using reactive ion, plasma, sputter etch or RIE technologies.
Claim 13
Dependent Claim
81 words
The method of claim 7 wherein said depositing a barrier layer over a surface of said hard mask layer thereby including inside surfaces of said trenches or openings is depositing a layer of material selected from a group containing titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN using rf sputtering of said barrier material whereby said barrier layer is preferably about 100 and 500 angstrom thick and more preferably about 300 angstrom thick.
Claim 14
Dependent Claim
92 words
The method of claim 7 wherein said depositing a seed layer over a surface of said barrier layer is using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr using copper or a copper alloy as a source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas whereby said seed layer is deposited to a minimum thickness of about 50 Angstrom.
Claim 15
Dependent Claim
37 words
The method of claim 7 wherein said polishing said layer of copper uses CMP techniques whereby said polishing of said layer of copper is continued to where a surface of said layer of dielectric is essentially reached.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-13 | 2005-02-12 | 2005-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-13 | 2009-02-12 | 2009-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-13 | 2013-02-12 | 2013-08-14 | $7700.00 | Window Closed / Lapsed |