← Back to Patent Explorer
US5933756A Expired / Lapsed US ⏱️ 0.0 years remaining

Fabrication process of a semiconductor device having a multilayered interconnection structure

Assignee: Ricoh Co Ltd
•
Filing: 1996-10-11
•
Granted: 1999-08-03
•
Expires: 2016-10-11
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of forming a multilayer interconnection structure includes the steps of forming a contact hole in an interlayer insulation film, depositing the contact hole by a conductive plug of a refractory element, applying a sputter-etching process to the interlayer insulation film to form a tapered part at a top part of the contact hole while using the conductive plug as an etching stopper, and filling the tapered part of the contact hole by a conductor material by a sputtering process.

Inventors

  • 👤 Akihiro Fuse

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 12:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/071; H10W20/081; H10W20/082

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 197 words
A method of fabricating a semiconductor device, said semiconductor device comprising a substrate and an interconnection structure provided on said substrate, said interconnection structure including an insulation film and a plurality of openings formed in said insulation film such that said openings extend from an upper major surface of said insulation film toward a lower major surface of said insulation film, said method comprising the steps of: (A) overfilling said openings by a conductive material and overetching such that said conductive material fills said openings from a bottom edge of said openings to a level below a top edge of said openings; (B) applying, after said step (A), a sputter-etching process to said insulation film, such that only an upper edge of each of said openings is removed, said contact hole thereby forming a tapered part above said level, such that a diameter of said openings increases continuously and gradually, in said tapered part, toward said upper major surface of said insulation film; (C) depositing, after said step (B), a conductor layer on said insulation film such that said conductor layer fills said tapered part of said openings in contact with said conductive material filling said openings.
Claim 2
Independent Claim 197 words
A method of fabricating a semiconductor device, said semiconductor device comprising a substrate and an interconnection structure provided on said substrate, said interconnection structure including an insulation film and a plurality of openings formed in said insulation film such that said openings extend from an upper major surface of said insulation film toward a lower major surface of said insulation film, said method comprising the steps of: (A) overfilling said openings by a conductive material and overetching such that said conductive material fills said openings from a bottom edge of said openings to a level below a top edge of said openings; (B) applying, after said step (A), a sputter-etching process to said insulation film, such that only an upper edge of each of said openings is removed, said contact hole thereby forming a tapered part above said level, such that a diameter of said openings increases continuously and gradually, in said tapered part, toward said upper major surface of said insulation film; (C) depositing, after said step (B), a conductor layer on said insulation film such that said conductor layer fills said tapered part of said openings in contact with said conductive material filling said openings.
Claim 3
Dependent Claim 20 words
A method as claimed in claim 1, wherein said step (A) fills said opening by W as said conductive material.
Claim 4
Dependent Claim 24 words
A method as claimed in claim 2, wherein said step of filling said opening by W is conducted by a vapor phase deposition process.
Claim 5
Dependent Claim 38 words
A method as claimed in claim 2, wherein said step (A) includes a step of covering said upper major surface of said insulation film by a conductive material containing a refractory element, before filling said opening by W.
Claim 6
Dependent Claim 34 words
A method as claimed in claim 4, wherein said step of covering said major surface of said insulation film includes a step of depositing TiN on said upper major surface of said insulation film.
Claim 7
Dependent Claim 34 words
A method as claimed in claim 1, wherein said step (C) includes a step of depositing a metal containing Al as a primary element as said conductor layer by a high temperature sputtering process.
Claim 8
Dependent Claim 31 words
A method as claimed in claim 1, wherein said step (B) and said step (C) are carried out commonly in a reaction chamber of a deposition apparatus including a plasma generator.
Claim 9
Dependent Claim 15 words
A method as claimed in claim 7, wherein said deposition apparatus is a sputtering apparatus.

References Cited (Backward Citations)

JPH02281757A Cited
US5091049A Cited
US4933297A Cited
JPH05121564A Cited
US5475266A Cited
CA2064922A1 Cited
US5371042A Cited
US5519239A Cited
US5286675A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-08-02 2003-02-01 2003-08-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-08-02 2007-02-01 2007-08-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-08-02 2011-02-01 2011-08-03 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag