Patent US6190977B1 successfully refreshed from Google Patents.
US6190977B1
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Method for forming MOSFET with an elevated source/drain
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-11-15
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Granted: 2001-02-20
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Expires: 2019-11-15
Abstract
Abstract A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:32
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01354; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/026; H10D30/60; H10D30/601; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D30/0212; H10D64/01304; H10D64/01306; H10D64/017; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
212 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an first dielectric layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region; doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region; forming an undoped spacer structure on sidewalls of said gate region; forming a second silicon layer on said semiconductor substrate; removing said first dielectric layer; doping said first silicon layer and said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; forming a metal layer over said semiconductor substrate; performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal silicide layer on said second silicon layer and said first silicon layer; and removing unreacted portion of said metal layer.
Claim 2
Independent Claim
212 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an first dielectric layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region; doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region; forming an undoped spacer structure on sidewalls of said gate region; forming a second silicon layer on said semiconductor substrate; removing said first dielectric layer; doping said first silicon layer and said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; forming a metal layer over said semiconductor substrate; performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal silicide layer on said second silicon layer and said first silicon layer; and removing unreacted portion of said metal layer.
Claim 3
Dependent Claim
39 words
The method of claim 1 , wherein said gate insulator layer comprises a silicon oxide layer which is thermally grown in an oxygen containing ambient from said semiconductor substrate with a thickness of about 15 angstroms to 300 angstroms.
Claim 4
Dependent Claim
27 words
The method of claim 1 , wherein said first silicon layer comprises an undoped polysilicon layer deposited with a thickness of about 300 angstroms to 4000 angstroms.
Claim 5
Dependent Claim
27 words
The method of claim 1 , wherein said first silicon layer comprises an doped polysilicon layer deposited with a thickness of about 300 angstroms to 4000 angstroms.
Claim 6
Dependent Claim
32 words
The method of claim 1 , wherein said first dielectric layer comprises a silicon oxide layer formed by a chemical vapor deposition to have a thickness between about 300 to 1500 angstroms.
Claim 7
Dependent Claim
15 words
The method of claim 1 , wherein said undoped spacer structure comprises silicon nitride spacers.
Claim 8
Dependent Claim
18 words
The method of claim 1 , wherein said second silicon layer is deposited with a selective epitaxial process.
Claim 9
Dependent Claim
23 words
The method of claim 1 , wherein said doping step for forming said extended source/drain junction is performed with a plasma immersion process.
Claim 10
Dependent Claim
34 words
The method of claim 1 , wherein said doping step for forming said extended source/drain regions is performed with a low energy ion implantation process with an energy between about 0.1 to 5 KeV.
Claim 11
Dependent Claim
23 words
The method of claim 1 , wherein said metal layer is selected from the group consisting of Ti, Co, W, Ni and Pt.
Claim 12
Dependent Claim
37 words
The method of claim 1 , wherein said thermal process for forming said metal silicide layer is performed with a rapid thermal process in a nitrogen ambient with a temperature of about 600° C. to 1,000° C.
Claim 13
Dependent Claim
41 words
The method of claim 1 , wherein said step of removing said uiireacted ortion of said metal layer is carried out by a wet etching of a solution containing H 4 OH, H 2 O, and H 2 O 2 .
Claim 14
Dependent Claim
31 words
The method of claim 1 further comprising the step of thermally growing a second dielectric layer on said substrate after said doping step for forming said extended source/drain regions is performed.
Claim 15
Independent Claim
270 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an first dielectric layer over said first silicon layer, said first dielectric layer comprising silicon oxide; removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region; doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region, with a low energy ion implantation process with an energy between about 0.1 to 5 KeV; thermally growing a second dielectric layer on said substrate and sidewalls of said first silicon layer; forming an undoped spacer structure on sidewalls of said gate region, said undoped spacer structure comprising silicon nitride spacers; forming a second silicon layer on said semiconductor substrate, said second silicon layer being deposited with a selective epitaxial process; removing said first dielectric layer; doping said first silicon layer and said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; forming a metal layer over said semiconductor substrate; performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal silicide layer on said second silicon layer and said first silicon layer; and removing unreacted portion of said metal layer.
Claim 16
Independent Claim
270 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an first dielectric layer over said first silicon layer, said first dielectric layer comprising silicon oxide; removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region; doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region, with a low energy ion implantation process with an energy between about 0.1 to 5 KeV; thermally growing a second dielectric layer on said substrate and sidewalls of said first silicon layer; forming an undoped spacer structure on sidewalls of said gate region, said undoped spacer structure comprising silicon nitride spacers; forming a second silicon layer on said semiconductor substrate, said second silicon layer being deposited with a selective epitaxial process; removing said first dielectric layer; doping said first silicon layer and said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure; forming a metal layer over said semiconductor substrate; performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal silicide layer on said second silicon layer and said first silicon layer; and removing unreacted portion of said metal layer.
Claim 17
Dependent Claim
39 words
The method of claim 14 , wherein said gate insulator layer comprises a silicon oxide layer which is thermally grown in an oxygen containing ambient from said semiconductor substrate with a thickness of about 15 angstroms to 300 angstroms.
Claim 18
Dependent Claim
27 words
The method of claim 14 , wherein said first silicon layer comprises an undoped polysilicon layer deposited with a thickness of about 300 angstroms to 4000 angstroms.
Claim 19
Dependent Claim
27 words
The method of claim 14 , wherein said first silicon layer comprises an doped polysilicon layer deposited with a thickness of about 300 angstroms to 4000 angstroms.
Claim 20
Dependent Claim
28 words
The method of claim 14 , wherein said first dielectric layer is formed by a chemical vapor deposition to have a thickness between about 300 to 1500 angstroms.
Claim 21
Dependent Claim
84 words
The method of claim 14 , wherein said removing said portion of gate insulator layer, of said first silicon layer, and of said first dielectric layer comprises the steps of: forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; and performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said first dielectric layer to define said gate region.
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