US5902125A
Expired / Lapsed
US
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Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-12-29
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Granted: 1999-05-11
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Expires: 2017-12-29
Abstract
Abstract The method includes forming a gate oxide on a substrate. A stacked-amorphous-silicon (SAS) layer is then formed on the gate oxide. An anti-reflective coating (ARC) layer is formed on the SAS layer. Next, a gate structure is patterned by etching. A silicon oxynitride layer is formed on the substrate, and covered the gate structure. A BSG sidewall spacers are formed on the side walls of the gate structure. A selective epitaxial silicon is grown on the substrate by using ultra high vacuum chemical vapor deposition. Then, an ARC layer is removed to expose the top of the SAS layer. Then, a blanket ion implantation is carried out to implant p type dopant into the SAS layer, the epitaxial silicon and silicon substrate. A SALICIDE layer, a polycide layer are respectively formed on the SAS layer and the epitaxial silicon. Further, the extended source and drain are formed in the step. A thick oxide layer is formed over the substrate and gate structure for isolation. Then, contact holes are generated in the oxide layer. Next, a metallization is carried out to form electrically connecting structure over the contact holes.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/027; H10D30/0275; H10D64/00; H10D64/01; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D30/0212; H10D64/017; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/952
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
243 words
A method for manufacturing a deep sub micron meter p type transistor on a semiconductor substrate, said method comprising the steps of: forming a gate oxide layer on said semiconductor substrate; forming a stacked-amorphous-silicon (SAS) layer on said gate oxide layer; forming an anti-reflective coating (ARC) layer on said SAS layer; patterning said ARC layer, said SAS layer, said gate oxide layer to form a gate structure; forming a first dielectric layer on said semiconductor substrate and said gate structure; forming a second dielectric layer having p type dopant on said first dielectric layer; etching said second dielectric layer to form sidewall spacers having p type dopant on sidewalls of said gate structure, a first portion of said first dielectric layer remaining between the gate structure and said side-wall spacers, a second portion of said first dielectric layer remaining under said side-wall spacers; selectively growing epitaxy silicon on said substrate that is uncovered by said gate structure, said sidewall spacers; removing said ARC layer; performing an ion implantation to doped p type dopant into said SAS layer, said epitaxy silicon and through said epitaxy silicon into said substrate; forming a conductive layer on said SAS layer, said epitaxy silicon and said sidewall spacers; and performing rapid thermal annealing (RTA) process to react said conductive layer with said epitaxy silicon, said SAS layer, thereby respectively forming self-aligned silicide and polycide thereon, and forming source and drain, extended source and drain under said sidewall spacers.
Claim 2
Independent Claim
243 words
A method for manufacturing a deep sub micron meter p type transistor on a semiconductor substrate, said method comprising the steps of: forming a gate oxide layer on said semiconductor substrate; forming a stacked-amorphous-silicon (SAS) layer on said gate oxide layer; forming an anti-reflective coating (ARC) layer on said SAS layer; patterning said ARC layer, said SAS layer, said gate oxide layer to form a gate structure; forming a first dielectric layer on said semiconductor substrate and said gate structure; forming a second dielectric layer having p type dopant on said first dielectric layer; etching said second dielectric layer to form sidewall spacers having p type dopant on sidewalls of said gate structure, a first portion of said first dielectric layer remaining between the gate structure and said side-wall spacers, a second portion of said first dielectric layer remaining under said side-wall spacers; selectively growing epitaxy silicon on said substrate that is uncovered by said gate structure, said sidewall spacers; removing said ARC layer; performing an ion implantation to doped p type dopant into said SAS layer, said epitaxy silicon and through said epitaxy silicon into said substrate; forming a conductive layer on said SAS layer, said epitaxy silicon and said sidewall spacers; and performing rapid thermal annealing (RTA) process to react said conductive layer with said epitaxy silicon, said SAS layer, thereby respectively forming self-aligned silicide and polycide thereon, and forming source and drain, extended source and drain under said sidewall spacers.
Claim 3
Dependent Claim
46 words
The method of claim 1, further comprises following steps after performing said RTA: forming an isolation layer on said gate structure, said semiconductor substrate; forming contact holes in said isolation layer; and forming an electrically connecting structure over said isolation layer and in said contact holes.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein said first dielectric layer comprises silicon oxynitride.
Claim 5
Dependent Claim
19 words
The method of claim 3, wherein said first dielectric layer is formed by oxidation in N 2 O ambient.
Claim 6
Dependent Claim
13 words
The method of claim 1, wherein said ARC layer comprises SiN x .
Claim 7
Dependent Claim
12 words
The method of claim 1, wherein said second dielectric layer comprises BSG.
Claim 8
Dependent Claim
14 words
The method of claim 1, wherein said SAS layer includes at least three sub-layers.
Claim 9
Dependent Claim
19 words
The method of claim 7, wherein the total thickness of said SAS layer is about 1000 to 4000 angstroms.
Claim 10
Dependent Claim
22 words
The method of claim 8, wherein the thickness of each said sub-layers of said SAS layer is respectively 500 to 1000 angstroms.
Claim 11
Dependent Claim
11 words
The method of claim 2, wherein said isolation layer comprises oxide.
Claim 12
Dependent Claim
20 words
The method of claim 1, wherein said epitaxy silicon is grown by ultra high vacuum chemical vapor deposition (UHV CVD).
Claim 13
Dependent Claim
18 words
The method of claim 1, wherein the thickness of said epitaxy silicon is about 300 to 1000 angstroms.
Claim 14
Dependent Claim
16 words
The method of claim 1, wherein said p type dopant for said ion implantation is boron.
Claim 15
Dependent Claim
18 words
The method of claim 1, wherein said p type dopant for said ion implantation is BF 2 .
Claim 16
Independent Claim
238 words
A method for manufacturing a deep sub micron meter p type transistor on a semiconductor substrate, said method comprising the steps of: forming a gate oxide layer on said semiconductor substrate; forming a stacked-amorphous-silicon (SAS) layer on said gate oxide layer; forming a SiN x layer on said SAS layer as an anti-reflective coating (ARC) layer; patterning said ARC layer, said SAS layer, said gate oxide layer to form a gate structure; forming a silicon oxynitride layer on said semiconductor substrate and said gate structure; forming a BSG layer on said silicon oxynitride layer; etching said BSG layer to form sidewall spacers on sidewalls of said gate structure, a first portion of said silicon oxynitride layer remaining between the gate structure and said side-wall spacers, a second portion of said silicon oxynitride layer remaining under said side-wall spacers; selectively growing epitaxy silicon on said substrate that is uncovered by said gate structure, said sidewall spacers; removing said ARC layer; performing an ion implantation to doped p type dopant into said SAS layer, said epitaxy silicon and through said epitaxy silicon into said substrate; forming a conductive layer on said SAS layer, said epitaxy silicon and said sidewall spacers; and performing rapid thermal annealing (RTA) process to react said conductive layer with said epitaxy silicon, said SAS layer, thereby respectively forming self-aligned silicide and polycide thereon, and forming source and drain, extended source and drain under said sidewall spacers.
Claim 17
Independent Claim
238 words
A method for manufacturing a deep sub micron meter p type transistor on a semiconductor substrate, said method comprising the steps of: forming a gate oxide layer on said semiconductor substrate; forming a stacked-amorphous-silicon (SAS) layer on said gate oxide layer; forming a SiN x layer on said SAS layer as an anti-reflective coating (ARC) layer; patterning said ARC layer, said SAS layer, said gate oxide layer to form a gate structure; forming a silicon oxynitride layer on said semiconductor substrate and said gate structure; forming a BSG layer on said silicon oxynitride layer; etching said BSG layer to form sidewall spacers on sidewalls of said gate structure, a first portion of said silicon oxynitride layer remaining between the gate structure and said side-wall spacers, a second portion of said silicon oxynitride layer remaining under said side-wall spacers; selectively growing epitaxy silicon on said substrate that is uncovered by said gate structure, said sidewall spacers; removing said ARC layer; performing an ion implantation to doped p type dopant into said SAS layer, said epitaxy silicon and through said epitaxy silicon into said substrate; forming a conductive layer on said SAS layer, said epitaxy silicon and said sidewall spacers; and performing rapid thermal annealing (RTA) process to react said conductive layer with said epitaxy silicon, said SAS layer, thereby respectively forming self-aligned silicide and polycide thereon, and forming source and drain, extended source and drain under said sidewall spacers.
Claim 18
Dependent Claim
19 words
The method of claim 15, wherein said SiN x layer is formed by oxidation in N 2 O ambient.
Claim 19
Dependent Claim
14 words
The method of claim 15, wherein said SAS layer includes at least three sub-layers.
Claim 20
Dependent Claim
19 words
The method of claim 17, wherein the total thickness of said SAS layer is about 1000 to 4000 angstroms.
Claim 21
Dependent Claim
22 words
The method of claim 18, wherein the thickness of each said sub-layers of said SAS layer is respectively 500 to 1000 angstroms.
Claim 22
Dependent Claim
20 words
The method of claim 15, wherein said epitaxy silicon is grown by ultra high vacuum chemical vapor deposition (UHV CVD).
Claim 23
Dependent Claim
18 words
The method of claim 15, wherein the thickness of said epitaxy silicon is about 300 to 1000 angstroms.
Claim 24
Dependent Claim
16 words
The method of claim 15, wherein said p type dopant for said ion implantation is boron.
Claim 25
Dependent Claim
18 words
The method of claim 15, wherein said p type dopant for said ion implantation is BF 2 .
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