US6046090A
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Process to fabricate ultra-short channel MOSFETS with self-aligned silicide contact
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-04-14
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Granted: 2000-04-04
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Expires: 2019-04-14
Abstract
Abstract The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A second silicon layer is formed over the first dielectric layer. Next, the second silicon layer is patterned to define a gate region. An etching process is performed to the second silicon layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual second silicon layer as a mask. The undoped polysilicon layer is etched by using the residual second silicon layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate. Next, a high dose arsenic or phosphorus ion implantation is performed through the metal layer to form first doped regions to serve as source and drain regions of the transistor. Finally, the two-step RTP annealing process is used to form self-aligned silicided contact of nMOSFETs.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:29
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/015; H10P30/21; H10P30/212; H10P30/28; H10D30/0212; H10D64/017; H10P32/00; H10P32/10; H10P32/12; H10P32/1204; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
237 words
A method for fabricating an ultra-short channel transistor in a semiconductor substrate with self-aligned silicide contact, said method comprising the steps of: forming a gate oxide layer on said substrate; forming a first silicon layer over said gate oxide layer; forming a first dielectric layer over said first silicon layer; forming a second silicon layer over said first dielectric layer; patterning said second silicon layer to define a gate region; performing an etching process to said second silicon layer to narrow a size of said gate region; etching portions of said first dielectric layer by using a residual second silicon layer as a mask; etching said first silicon layer by using said residual second silicon layer and said residual first dielectric layer as a mask; removing said residual second silicon layer; forming a second dielectric layer over said residual first dielectric layer and said substrate; etching said second dielectric layer to form side-wall spacers to serve as an ion diffusion source; removing said residual first dielectric layer; forming a metal layer on the surface of said side-wall spacers, said residual first silicon layer, and said substrate; performing an ion implantation through said substrate to form first doped regions to serve as source and drain regions of said transistor; and performing a first thermal annealing to form a metal silicide layer on a surface of said substrate and on a top surface of said residual first silicon layer.
Claim 2
Independent Claim
237 words
A method for fabricating an ultra-short channel transistor in a semiconductor substrate with self-aligned silicide contact, said method comprising the steps of: forming a gate oxide layer on said substrate; forming a first silicon layer over said gate oxide layer; forming a first dielectric layer over said first silicon layer; forming a second silicon layer over said first dielectric layer; patterning said second silicon layer to define a gate region; performing an etching process to said second silicon layer to narrow a size of said gate region; etching portions of said first dielectric layer by using a residual second silicon layer as a mask; etching said first silicon layer by using said residual second silicon layer and said residual first dielectric layer as a mask; removing said residual second silicon layer; forming a second dielectric layer over said residual first dielectric layer and said substrate; etching said second dielectric layer to form side-wall spacers to serve as an ion diffusion source; removing said residual first dielectric layer; forming a metal layer on the surface of said side-wall spacers, said residual first silicon layer, and said substrate; performing an ion implantation through said substrate to form first doped regions to serve as source and drain regions of said transistor; and performing a first thermal annealing to form a metal silicide layer on a surface of said substrate and on a top surface of said residual first silicon layer.
Claim 3
Dependent Claim
45 words
The method of claim 1 further comprising the step of etching non-reacted portions of said metal layer, thereby leaving said metal silicide on the top surface of said residual first silicon layer and on the source and drain regions after said first thermal annealing process.
Claim 4
Dependent Claim
20 words
The method of claim 2 further comprising the step of performing a second thermal annealing, after etching said metal layer.
Claim 5
Dependent Claim
25 words
The method of claim 3, wherein said second thermal annealing is performed at a temperature about 700 to 1150 Centigrade degree for about 10-100 seconds.
Claim 6
Dependent Claim
15 words
The method of claim 1, wherein said first silicon layer is an undoped polysilicon layer.
Claim 7
Dependent Claim
19 words
The method of claim 5, wherein said undoped polysilicon layer has a thickness of about 500 to 3000 angstroms.
Claim 8
Dependent Claim
24 words
The method of claim 1, wherein said first dielectric layer is selected from the group consisting of silicon oxynitride, silicon oxide and silicon nitride.
Claim 9
Dependent Claim
19 words
The method of claim 1, wherein said first dielectric layer has a thickness of about 100 to 2000 angstroms.
Claim 10
Dependent Claim
22 words
The method of claim 1, wherein said second silicon layer is selected from the group consisting of undoped polysilicon and doped polysilicon.
Claim 11
Dependent Claim
19 words
The method of claim 1, wherein said second silicon layer has a thickness of about 500 to 3000 angstroms.
Claim 12
Dependent Claim
21 words
The method of claim 1, wherein said etching process to said second silicon layer is performed by an isotropic dry etching.
Claim 13
Dependent Claim
17 words
The method of claim 1, wherein said second dielectric layer is a phosphosilicate glass (PSG) oxide layer.
Claim 14
Dependent Claim
17 words
The method of claim 12, wherein said PSG layer have a thickness about 200 to 1500 angstroms.
Claim 15
Dependent Claim
22 words
The method of claim 1, wherein said ion implantation has a dosage of about 5×10 14 to 5×10 16 ions/cm 2 .
Claim 16
Dependent Claim
25 words
The method of claim 1, wherein said first thermal annealing is performed at a temperature about 300 to 700 Centigrade degree for about 30-180 seconds.
Claim 17
Independent Claim
287 words
A method for fabricating an ultra-short channel transistor in a semiconductor substrate with self-aligned silicide contact, said method comprising the steps of: forming a gate oxide layer on said substrate; forming a first silicon layer over said gate oxide layer; forming a first dielectric layer over said first silicon layer, said first dielectric layer being selected from the group consisting of silicon oxynitride and silicon oxide; forming a second silicon layer over said first dielectric layer; patterning said second silicon layer to define a gate region; performing an etching process to said second silicon layer to narrow a size of said gate region; etching portions of said first dielectric layer by using a residual second silicon layer as a mask; etching said first silicon layer by using said residual second silicon layer and said residual first dielectric layer as a mask; removing said residual second silicon layer; forming a second dielectric layer over said residual first dielectric layer and said substrate; etching said second dielectric layer to form side-wall spacers to serve as an ion diffusion source; removing said residual first dielectric layer; forming a metal layer on the surface of said side-wall spacers, said residual first silicon layer, and said substrate; performing an ion implantation through said substrate to form first doped regions to serve as source and drain regions of said transistor; performing a first thermal annealing to form a metal silicide layer on a surface of said substrate and on a top surface of said residual first silicon layer; etching non-reacted portions of said metal layer, thereby leaving said metal silicide on the top surface of said residual first silicon layer and on the source and drain regions; and performing a second thermal annealing.
Claim 18
Independent Claim
287 words
A method for fabricating an ultra-short channel transistor in a semiconductor substrate with self-aligned silicide contact, said method comprising the steps of: forming a gate oxide layer on said substrate; forming a first silicon layer over said gate oxide layer; forming a first dielectric layer over said first silicon layer, said first dielectric layer being selected from the group consisting of silicon oxynitride and silicon oxide; forming a second silicon layer over said first dielectric layer; patterning said second silicon layer to define a gate region; performing an etching process to said second silicon layer to narrow a size of said gate region; etching portions of said first dielectric layer by using a residual second silicon layer as a mask; etching said first silicon layer by using said residual second silicon layer and said residual first dielectric layer as a mask; removing said residual second silicon layer; forming a second dielectric layer over said residual first dielectric layer and said substrate; etching said second dielectric layer to form side-wall spacers to serve as an ion diffusion source; removing said residual first dielectric layer; forming a metal layer on the surface of said side-wall spacers, said residual first silicon layer, and said substrate; performing an ion implantation through said substrate to form first doped regions to serve as source and drain regions of said transistor; performing a first thermal annealing to form a metal silicide layer on a surface of said substrate and on a top surface of said residual first silicon layer; etching non-reacted portions of said metal layer, thereby leaving said metal silicide on the top surface of said residual first silicon layer and on the source and drain regions; and performing a second thermal annealing.
Claim 19
Dependent Claim
15 words
The method of claim 16, wherein said first silicon layer is an undoped polysilicon layer.
Claim 20
Dependent Claim
22 words
The method of claim 16, wherein said second silicon layer is selected from the group consisting of undoped polysilicon and doped polysilicon.
Claim 21
Dependent Claim
21 words
The method of claim 16, wherein said etching process to said second silicon layer is performed by an isotropic dry etching.
Claim 22
Dependent Claim
17 words
The method of claim 16, wherein said second dielectric layer is a phosphosilicate glass (PSG) oxide layer.
References Cited (Backward Citations)
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