Semiconductor device having a multilayered interconnection structure

Claim 1

A fabrication process of a semiconductor device, comprising the steps of: forming a first insulation film over a substrate; forming a second insulation film of an organic material over said first interlayer insulation film; forming a first etching stopper film on said second interlayer insulation film; forming a second, different etching stopper film on said first etching stopper film; forming a first opening in said second etching stopper film so as to expose said first etching stopper film; forming a second opening in a part of said first etching stopper film exposed by said first opening; forming a third opening in said second insulation film in correspondence to said second opening by applying an etching process while using said first etching stopper film as a mask; forming an interconnection groove in said second insulation film in correspondence to said first opening by applying an etching process while using said second etching stopper film as a mask; forming a contact hole in said first insulation film in correspondence to said third opening; and filling said contact hole and said interconnection groove by a conductive material.