Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process

Claim 2

A semiconductor integrated circuit device fabrication method comprising: (a) exposing a first photoresist film of one of positive or negative photoresists over a major surface of a wafer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (b) forming a first pattern over the major surface of the wafer by using the patterned first photoresist film; (c) prior to step (a) or after step (b), exposing a second photoresist film of the other of the positive or negative photoresists over the major surface of the wafer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (d) forming a second pattern over the major surface of the wafer by using the patterned second photoresist film; (e) exposing a third photoresist film over the major surface of the wafer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (f) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 3

A semiconductor integrated circuit device fabrication method according to claim 1, wherein the first photoresist film is a negative photoresist.

Claim 4

A semiconductor integrated circuit device fabrication method according to claim 2, wherein the third photoresist film is a positive photoresist.

Claim 5

A semiconductor integrated circuit device fabrication method according to claim 2, wherein the first and second transmission regions are isolated from each other with a light shielding region over the major surface of the first mask.

Claim 6

A semiconductor integrated circuit device fabrication method according to claim 4, wherein the first and second transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 7

A semiconductor integrated circuit device fabrication method according to claim 5, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 8

A semiconductor integrated circuit device fabrication method according to claim 5, wherein the third and fourth transmission regions border on each other over the major surface of the second mask.

Claim 9

A semiconductor integrated circuit device fabrication method according to claim 7, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 10

A semiconductor integrated circuit device fabrication method according to claim 5, wherein the third and fourth transmission regions are isolated from each other with a light shielding region over the major surface of the second mask.

Claim 11

A semiconductor integrated circuit device fabrication method according to claim 9, wherein the third and fourth transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 12

A semiconductor integrated circuit device fabrication method according to claim 9, wherein the third transmission region is a principal transmission region corresponding to a hole pattern over the major surface of the wafer, and the fourth transmission region is one of a plurality of auxiliary opening regions disposed around the principal transmission region.

Claim 13

A semiconductor integrated circuit device fabrication method according to claim 11, wherein the second pattern over the wafer is a hole pattern.

Claim 14

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer corresponding to a line and space pattern over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (f) forming a second pattern corresponding to a hole pattern in the second layer over the major surface of the wafer by using the patterned second photoresist film; (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 15

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer corresponding to a line and space pattern over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (f) forming a second pattern corresponding to a hole pattern in the second layer over the major surface of the wafer by using the patterned second photoresist film; (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 16

A semiconductor integrated circuit device fabrication method according to claim 13, wherein the third photoresist film is a positive photoresist.

Claim 17

A semiconductor integrated circuit device fabrication method according to claim 13, wherein the first and second transmission regions are isolated from each other with a light shielding region over the major surface of the first mask.

Claim 18

A semiconductor integrated circuit device fabrication method according to claim 15, wherein the third and fourth transmission regions border on each other over the major surface of the second mask.

Claim 19

A semiconductor integrated circuit device fabrication method according to claim 15, wherein the third and fourth transmission regions are isolated from each other with a light shielding region over the major surface of the second mask.

Claim 20

A semiconductor integrated circuit device fabrication method according to claim 17, wherein the third and fourth transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 21

A semiconductor integrated circuit device fabrication method according to claim 17, wherein the third transmission region is a principal transmission region corresponding to a hole pattern over the major surface of the wafer, and the fourth transmission region is one of a plurality of auxiliary transmission regions disposed around the principal transmission region.

Claim 22

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer corresponding to a line and space pattern over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a principal transmission region and an auxiliary transmission region outside the principal transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (f) forming a second pattern corresponding to a hole pattern in the second layer over the major surface of the wafer by using the patterned second photoresist film; (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 23

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer corresponding to a line and space pattern over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a principal transmission region and an auxiliary transmission region outside the principal transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (f) forming a second pattern corresponding to a hole pattern in the second layer over the major surface of the wafer by using the patterned second photoresist film; (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 24

A semiconductor integrated circuit device fabrication method according to claim 20, wherein the third photoresist film is a positive photoresist.

Claim 25

A semiconductor integrated circuit device fabrication method according to claim 20, wherein the first and second transmission regions are isolated from each other with a light shielding region over the major surface of the first mask.

Claim 26

A semiconductor integrated circuit device fabrication method according to claim 22, wherein the principal and auxiliary transmission regions border on each other over the major surface of the second mask.

Claim 27

A semiconductor integrated circuit device fabrication method according to claim 22, wherein the principal and auxiliary transmission regions are isolated from each other with a light shielding region over the major surface of the second mask.

Claim 28

A semiconductor integrated circuit device fabrication method according to claim 24, wherein the principal transmission region corresponds to a hole pattern over the major surface of the wafer, and the auxiliary transmission region is one of a plurality of auxiliary opening regions disposed around the principal transmission region.

Claim 29

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first principal transmission region corresponding to a pattern to be transferred onto the wafer and a first auxiliary transmission region, to transmit an auxiliary exposure light beam, outside the first principal transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer corresponding to a line and space pattern over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a second principal transmission region corresponding to a pattern to be transferred onto the wafer and a second auxiliary transmission region, to transmit an auxiliary exposure light beam, outside the second principal transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (f) forming a second pattern corresponding to a hole pattern in the second layer over the major surface of the wafer by using the patterned second photoresist film; (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 30

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first principal transmission region corresponding to a pattern to be transferred onto the wafer and a first auxiliary transmission region, to transmit an auxiliary exposure light beam, outside the first principal transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer corresponding to a line and space pattern over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a second principal transmission region corresponding to a pattern to be transferred onto the wafer and a second auxiliary transmission region, to transmit an auxiliary exposure light beam, outside the second principal transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; (f) forming a second pattern corresponding to a hole pattern in the second layer over the major surface of the wafer by using the patterned second photoresist film; (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 31

A semiconductor integrated circuit device fabrication method according to claim 26, wherein the third photoresist film is a positive photoresist.

Claim 32

A semiconductor integrated circuit device fabrication method according to claim 26, wherein the first principal and auxiliary transmission regions are isolated from each other with a light shielding region over the major surface of the first mask.

Claim 33

A semiconductor integrated circuit device fabrication method according to claim 28, wherein the second principal and auxiliary transmission regions border on each other over the major surface of the second mask.

Claim 34

A semiconductor integrated circuit device fabrication method according to claim 28, wherein the second principal and auxiliary transmission regions are isolated from each other with a light shielding region over the major surface of the second mask.

Claim 35

A semiconductor integrated circuit device fabrication method according to claim 30, wherein the second principal transmission region corresponds to a hole pattern over the major surface of the wafer, and the second auxiliary transmission region is one of a plurality of auxiliary opening regions disposed around the principal transmission region.

Claim 36

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second ask; and (f) forming a second pattern of the second layer over the major surface of the wafer by using the patterned second photoresist film.

Claim 37

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second ask; and (f) forming a second pattern of the second layer over the major surface of the wafer by using the patterned second photoresist film.

Claim 38

A semiconductor integrated circuit device fabrication method according to claim 32, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 39

A semiconductor integrated circuit device fabrication method according to claim 33, wherein the third photoresist film is a positive photoresist.

Claim 40

A semiconductor integrated circuit device fabrication method according to claim 32, wherein the first and second transmission regions are isolated from each other with a light shielding region over the major surface of the first mask.

Claim 41

A semiconductor integrated circuit device fabrication method according to claim 35, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 42

A semiconductor integrated circuit device fabrication method according to claim 35, wherein the first and second transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 43

A semiconductor integrated circuit device fabrication method according to claim 37, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 44

A semiconductor integrated circuit device fabrication method according to claim 37, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 45

A semiconductor integrated circuit device fabrication method according to claim 39, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 46

A semiconductor integrated circuit device fabrication method according to claim 37, wherein the third and fourth transmission regions border on each other over the major surface of the second mask.

Claim 47

A semiconductor integrated circuit device fabrication method according to claim 41, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 48

A semiconductor integrated circuit device fabrication method according to claim 41, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 49

A semiconductor integrated circuit device fabrication method according to claim 43, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 50

A semiconductor integrated circuit device fabrication method according to claim 37, wherein the third and fourth transmission regions are isolated from each other with a light shielding region over the major surface of the second mask.

Claim 51

A semiconductor integrated circuit device fabrication method according to claim 45, wherein the third transmission region is a principal transmission region corresponding to a hole pattern over the major surface of the wafer, and the fourth transmission region is one of a plurality of auxiliary opening regions disposed around the principal transmission region.

Claim 52

A semiconductor integrated circuit device fabrication method according to claim 46, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 53

A semiconductor integrated circuit device fabrication method according to claim 46, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 54

A semiconductor integrated circuit device fabrication method according to claim 48, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 55

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a first mask; (c) forming a first pattern of the first layer over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a second mask; and (f) forming a second pattern of the second layer over the major surface of the wafer by using the patterned second photoresist film, the first mask comprising: (i) a first transparent substrate having a major surface; (ii) a first light shielding region disposed over the major surface of the first transparent substrate; (iii) a first transmission region in the first light shielding region; and (iv) a second transmission region outside the first transmission region in the first light shielding region, which second transmission region constitutes a first integrated circuit pattern together with the first transmission region on the major surface of the first transparent substrate, the phase of exposure light beam transmitted through the second transmission region being inverted as compared with that of exposure light beam transmitted through the first transmission region, and the second mask comprising: (i) a second transparent substrate having a major surface; (ii) a second light shielding region disposed over the major surface of the second transparent substrate; (iii) a third transmission region in the second light shielding region; and (iv) a fourth transmission region outside the third transmission region in the second light shielding region, which fourth transmission region constitutes a second integrated circuit pattern together with the third transmission region on the major surface of the second transparent substrate, the phase of exposure light beam transmitted through the fourth transmission region being inverted as compared with that of exposure light beam transmitted through the third transmission region.

Claim 56

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a first mask; (c) forming a first pattern of the first layer over the major surface of the wafer by using the patterned first photoresist film; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a second mask; and (f) forming a second pattern of the second layer over the major surface of the wafer by using the patterned second photoresist film, the first mask comprising: (i) a first transparent substrate having a major surface; (ii) a first light shielding region disposed over the major surface of the first transparent substrate; (iii) a first transmission region in the first light shielding region; and (iv) a second transmission region outside the first transmission region in the first light shielding region, which second transmission region constitutes a first integrated circuit pattern together with the first transmission region on the major surface of the first transparent substrate, the phase of exposure light beam transmitted through the second transmission region being inverted as compared with that of exposure light beam transmitted through the first transmission region, and the second mask comprising: (i) a second transparent substrate having a major surface; (ii) a second light shielding region disposed over the major surface of the second transparent substrate; (iii) a third transmission region in the second light shielding region; and (iv) a fourth transmission region outside the third transmission region in the second light shielding region, which fourth transmission region constitutes a second integrated circuit pattern together with the third transmission region on the major surface of the second transparent substrate, the phase of exposure light beam transmitted through the fourth transmission region being inverted as compared with that of exposure light beam transmitted through the third transmission region.

Claim 57

A semiconductor integrated circuit device fabrication method according to claim 50, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 58

A semiconductor integrated circuit device fabrication method according to claim 51, wherein the third photoresist film is a positive photoresist.

Claim 59

A semiconductor integrated circuit device fabrication method according to claim 50, wherein the first and second transmission regions are isolated from each other with a first light shielding region over the major surface of the first transparent substrate.

Claim 60

A semiconductor integrated circuit device fabrication method according to claim 53, wherein the first and second transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 61

A semiconductor integrated circuit device fabrication method according to claim 54, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 62

A semiconductor integrated circuit device fabrication method according to claim 54, wherein the third and fourth transmission regions border on each other over the major surface of the second transparent substrate.

Claim 63

A semiconductor integrated circuit device fabrication method according to claim 56, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 64

A semiconductor integrated circuit device fabrication method according to claim 56, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 65

A semiconductor integrated circuit device fabrication method according to claim 58, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 66

A semiconductor integrated circuit device fabrication method according to claim 54, wherein the third and fourth transmission regions are isolated from each other with a second light shielding region over the major surface of the second transparent substrate.

Claim 67

A semiconductor integrated circuit device fabrication method according to claim 60, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 68

A semiconductor integrated circuit device fabrication method according to claim 60, wherein the third and fourth transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 69

A semiconductor integrated circuit device fabrication method according to claim 62, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phasing-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 70

A semiconductor integrated circuit device fabrication method according to claim 60, wherein the third transmission region is a principal transmission region corresponding to a hole pattern over the major surface of the wafer, and the fourth transmission region is one of a plurality of auxiliary opening regions disposed around the principal transmission region.

Claim 71

A semiconductor integrated circuit device fabrication method according to claim 64, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 72

A semiconductor integrated circuit device fabrication method according to claim 64, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 73

A semiconductor integrated circuit device fabrication method according to claim 66, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 74

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer over the major surface of the wafer by using the patterned first photoresist film, which first pattern is a set of simply connected figures having no internal openings; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; and (f) forming a second pattern of the second layer over the major surface of the wafer by using the patterned second photoresist film, which second pattern is a set of simply connected openings having no internal figures.

Claim 75

A semiconductor integrated circuit device fabrication method comprising: (a) forming a first layer over a major surface of a wafer; (b) exposing a first photoresist film of a negative photoresist over the first layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a first transmission region and a second transmission region outside the first transmission region on a major surface of a first mask, which constitute a first integrated circuit pattern on the major surface of the first mask; (c) forming a first pattern of the first layer over the major surface of the wafer by using the patterned first photoresist film, which first pattern is a set of simply connected figures having no internal openings; (d) prior to step (a) or after step (c), forming a second layer over the major surface of the wafer; (e) exposing a second photoresist film of a positive photoresist over the second layer, by phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams, the phases of which are inverted with respect to each other as a result of being transmitted through a third transmission region and a fourth transmission region outside the third transmission region on a major surface of a second mask, which constitute a second integrated circuit pattern on the major surface of the second mask; and (f) forming a second pattern of the second layer over the major surface of the wafer by using the patterned second photoresist film, which second pattern is a set of simply connected openings having no internal figures.

Claim 76

A semiconductor integrated circuit device fabrication method according to claim 68, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 77

A semiconductor integrated circuit device fabrication method according to claim 69, wherein the third photoresist film is a positive photoresist.

Claim 78

A semiconductor integrated circuit device fabrication method according to claim 68, wherein the first and second transmission regions are isolated from each other with a light shielding region over the major surface of the first mask.

Claim 79

A semiconductor integrated circuit device fabrication method according to claim 71, wherein the first and second transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 80

A semiconductor integrated circuit device fabrication method according to claim 72, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 81

A semiconductor integrated circuit device fabrication method according to claim 72, wherein the third and fourth transmission regions border on each other over the major surface of the second mask.

Claim 82

A semiconductor integrated circuit device fabrication method according to claim 74, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 83

A semiconductor integrated circuit device fabrication method according to claim 74, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 84

A semiconductor integrated circuit device fabrication method according to claim 76, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 85

A semiconductor integrated circuit device fabrication method according to claim 72, wherein the third and fourth transmission regions are isolated from each other with a light shielding region over the major surface of the second mask.

Claim 86

A semiconductor integrated circuit device fabrication method according to claim 78, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 87

A semiconductor integrated circuit device fabrication method according to claim 78, wherein the third and fourth transmission regions respectively correspond to patterns over the major surface of the wafer.

Claim 88

A semiconductor integrated circuit device fabrication method according to claim 80, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 89

A semiconductor integrated circuit device fabrication method according to claim 78, wherein the third transmission region is a principal transmission region corresponding to a hole pattern over the major surface of the wafer, and the fourth transmission region is one of a plurality of auxiliary opening regions disposed around the principal transmission region.

Claim 90

A semiconductor integrated circuit device fabrication method according to claim 82, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern non a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.

Claim 91

A semiconductor integrated circuit device fabrication method according to claim 82, wherein the second pattern over the major surface of the wafer is a hole pattern.

Claim 92

A semiconductor integrated circuit device fabrication method according to claim 84, further comprising: (g) forming a third layer over the major surface of the wafer; (h) exposing a third photoresist film over the third layer, by non-phase-shifting exposure with optical reduction projection, to ultraviolet or deep ultraviolet exposure light beams transmitted through a third integrated circuit pattern on a major surface of a third mask; and (i) forming a third pattern over the major surface of the wafer by using the patterned third photoresist film.