US4592132A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating multi-level-metal integrated circuits at high yields
Assignee: Raytheon Co
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Filing: 1984-12-07
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Granted: 1986-06-03
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Expires: 2004-12-07
Abstract
Abstract Inter-layer electrical shorting between layers of conductors of an integrated circuit caused by "hillocks" in the bottom layer is prevented by the use of a double layer photoresist coatings atop the insulating layer that separates the metal layers. The double layer photoresist insures that irregularities in the dielectric layer caused by hillocks in the underlying insulating layer do not cause a break in the photoresist and a subsequent undesired etching of a spurious "via" through the dielectric layer.
Inventors
- 👤 William W. Y. Lee
- 👤 Gareth L. Shaw
- 👤 James W. Clayton, deceased
- 👤 administrator Denise Bachino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:45
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/031; H10W20/056; H10W20/081; H10W20/093; H10W20/096; H10W20/40; H10W20/41; H10W20/435
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
144 words
In a process for fabricating multi-level metal integrated circuits wherein at least first and second layers of metal are deposited above a semiconductor substrate and are separated there by an inter-layer dielectric material, the improvement comprising: forming a relatively thick photoresist coating atop said inter-layer dielectric by initially forming a first layer of photoresist on the surface of said inter-layer dielectric, then treating said first layer in a manner that makes it substantially impervious to photoresist solvents, and then forming a second layer of photoresist atop said first layer of photoresist to a thickness sufficient to cover vertical protrusions in said inter-layer dielectric resulting from hillocks or spikes in said first layer of metal, whereby the multilayer photoresist coating maintains its thickness and conformity with said inter-layer dielectric, thereby preventing electrical shorts between said first and second metal layers and enhancing process fabrication yields.
Claim 2
Dependent Claim
144 words
In a process for fabricating multi-level metal integrated circuits wherein at least first and second layers of metal are deposited above a semiconductor substrate and are separated there by an inter-layer dielectric material, the improvement comprising: forming a relatively thick photoresist coating atop said inter-layer dielectric by initially forming a first layer of photoresist on the surface of said inter-layer dielectric, then treating said first layer in a manner that makes it substantially impervious to photoresist solvents, and then forming a second layer of photoresist atop said first layer of photoresist to a thickness sufficient to cover vertical protrusions in said inter-layer dielectric resulting from hillocks or spikes in said first layer of metal, whereby the multilayer photoresist coating maintains its thickness and conformity with said inter-layer dielectric, thereby preventing electrical shorts between said first and second metal layers and enhancing process fabrication yields.
Claim 3
Dependent Claim
49 words
The process defined in claim 1 wherein said first layer of photoresist substantially is exposed to a gas plasma at a predetermined pressure and predetermined elevated temperature for a time sufficient to render said first layer of photoresist impervious to solvents in a subsequently applied second layer of photoresist.
Claim 4
Dependent Claim
135 words
In a process for fabricating multi-level metal integrated circuits wherein at least first and second layers of metal are deposited above a semiconductor substrate and are separated there by an inter-layer dielectric, the improvement comprising: forming a complete photoresist coating by forming both negative and positive layers of photoresist atop said inter-layer dielectric to a thickness sufficient to cover any vertical protrusions in said inter-layer dielectric produced by hillocks or spikes in said first metal layer, said negative and positive photoresist layers including different solvents that do not significantly interact with or harm the respective negative or positive photoresist layers, thereby enabling said composite photoresist coating to maintain its thickness and conformity with said inter-layer dielectric and prevent electrical shorts between said first and second metal layers, whereby fabrication yields of said process are enhanced.
Claim 5
Dependent Claim
135 words
In a process for fabricating multi-level metal integrated circuits wherein at least first and second layers of metal are deposited above a semiconductor substrate and are separated there by an inter-layer dielectric, the improvement comprising: forming a complete photoresist coating by forming both negative and positive layers of photoresist atop said inter-layer dielectric to a thickness sufficient to cover any vertical protrusions in said inter-layer dielectric produced by hillocks or spikes in said first metal layer, said negative and positive photoresist layers including different solvents that do not significantly interact with or harm the respective negative or positive photoresist layers, thereby enabling said composite photoresist coating to maintain its thickness and conformity with said inter-layer dielectric and prevent electrical shorts between said first and second metal layers, whereby fabrication yields of said process are enhanced.
Claim 6
Dependent Claim
51 words
The process defined in claim 3 wherein said negative photoresist layer is a negative resist polymer and said positive photoresist layer is a positive resist polymer, and said polymers are deposited and baked-on sequentially for predetermined baking times and temperatures sufficient to render them impervious to attack by certain photoresist solvents.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |