Patent US6121666A successfully refreshed from Google Patents.
US6121666A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Split gate oxide asymmetric MOS devices
Assignee: Oracle America Inc
•
Filing: 1997-06-27
•
Granted: 2000-09-19
•
Expires: 2017-06-27
Abstract
Abstract A method for making an asymmetric MOS device having a notched gate oxide is disclosed herein. Such MOS devices have a region of a gate oxide adjacent to either the source or drain that is thinner than the remainder of the gate oxide. The thin "notched" region of gate oxide lies over a region of the device's channel region that has been engineered to have a relatively "high" threshold voltage (near 0 volts) in comparison to the remainder of the channel region. This region of higher threshold voltage may be created by a pocket region of increased dopant concentration abutting the source or the drain (but not both) and proximate the channel region. The pocket region has the opposite conductivity type as the source and drain. A device so structured behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket region is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET. If the pocket region is located under the drain, the reverse arrangement will be true. The region of thin gate oxide (the notched region) provides a higher gate capacitance than the remaining regions of thicker gate oxide. Thus, the channel region under the notched region of gate oxide has a relatively high concentration of mobile charge carriers in the channel region.
Inventors
- 👤 James B. Burr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D62/351; H10D62/357; H10D62/364; H10D62/371
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
342 words
An asymmetric MOS device on a semiconductor substrate having an active surface, the asymmetric MOS device comprising: a bulk region in the semiconductor substrate of a first conductivity type; source and drain regions positioned within said bulk region and being of a second conductivity type; a channel region located along said substrate active surface and between the source and drain regions, the channel region having an associated channel length representing the distance in said channel region between the source and drain regions; a gate dielectric layer positioned over the channel region and having a notch region over a portion of the channel region; and a gate electrode positioned over the gate dielectric, the gate electrode having a first lateral section of said first conductivity type and having a second lateral section of said second conductivity type, said first lateral section having a first lateral section length which extends parallel to said substrate active surface and a first lateral section height which extends perpendicular to said substrate active surface, said second lateral section having a second lateral section length which extends parallel to said substrate active surface and a second lateral section height which extends perpendicular to said substrate active surface, wherein said first lateral section length is shorter than said second lateral section length and said first lateral section height is higher than said second lateral section height and further wherein, a junction between said first and second lateral sections is located over said channel region between said source and drain regions such that a first portion of said channel region underlying said first lateral section has a locally high threshold voltage and a second portion of said channel region underlying said second lateral section has a locally low threshold voltage, said first portion of said channel region having a first portion length which extends parallel to said substrate active surface which is shorter than a second portion length of said second portion of said channel region which extends parallel to said substrate active surface so as to define an asymmetric channel.
Claim 2
Dependent Claim
342 words
An asymmetric MOS device on a semiconductor substrate having an active surface, the asymmetric MOS device comprising: a bulk region in the semiconductor substrate of a first conductivity type; source and drain regions positioned within said bulk region and being of a second conductivity type; a channel region located along said substrate active surface and between the source and drain regions, the channel region having an associated channel length representing the distance in said channel region between the source and drain regions; a gate dielectric layer positioned over the channel region and having a notch region over a portion of the channel region; and a gate electrode positioned over the gate dielectric, the gate electrode having a first lateral section of said first conductivity type and having a second lateral section of said second conductivity type, said first lateral section having a first lateral section length which extends parallel to said substrate active surface and a first lateral section height which extends perpendicular to said substrate active surface, said second lateral section having a second lateral section length which extends parallel to said substrate active surface and a second lateral section height which extends perpendicular to said substrate active surface, wherein said first lateral section length is shorter than said second lateral section length and said first lateral section height is higher than said second lateral section height and further wherein, a junction between said first and second lateral sections is located over said channel region between said source and drain regions such that a first portion of said channel region underlying said first lateral section has a locally high threshold voltage and a second portion of said channel region underlying said second lateral section has a locally low threshold voltage, said first portion of said channel region having a first portion length which extends parallel to said substrate active surface which is shorter than a second portion length of said second portion of said channel region which extends parallel to said substrate active surface so as to define an asymmetric channel.
Claim 3
Dependent Claim
17 words
The asymmetric MOS device of claim 1 wherein the first and second lateral sections are degenerately doped.
Claim 4
Dependent Claim
22 words
The asymmetric MOS device of claim 1 wherein the channel region is counter doped with a dopant of the second conductivity type.
Claim 5
Dependent Claim
21 words
The asymmetric MOS device of claim 1 wherein the first lateral section is no more than about 0.1 μm in length.
Claim 6
Dependent Claim
23 words
The asymmetric MOS device of claim 1 wherein the gate dielectric layer has a notch region over a portion of the channel region.
Claim 7
Dependent Claim
21 words
The asymmetric MOS device of claim 1 wherein the first lateral section overlies the notch region of the gate dielectric layer.
Claim 8
Dependent Claim
43 words
The asymmetric MOS device of claim 1 further comprising a buried electrode of said first conductivity type located beneath the channel region, wherein said buried electrode has an average dopant concentration which is greater than an average dopant concentration of the bulk region.
Claim 9
Dependent Claim
62 words
The asymmetric MOS device of claim 1 further comprising a pocket region of the first conductivity type, the pocket region abutting one of said source or drain regions and proximate said channel region, the pocket region having an average concentration of dopant atoms of the first conductivity type, which average concentration is greater than the bulk region's average concentration of dopant atoms.
References Cited (Backward Citations)
US3719866A
Cited
US3877055A
Cited
US4939571A
Cited
US4173818A
Cited
JPS59124161A
Cited
US4949140A
Cited
US5031008A
Cited
US5422505A
Cited
US5567629A
Cited
US5658811A
Cited
US5780912A
Cited
US5536959A
Cited
US5801416A
Cited
US5753952A
Cited
US5780902A
Cited
US5744994A
Cited
US5741737A
Cited
US5766998A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-19 | 2004-03-20 | 2004-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-19 | 2008-03-20 | 2008-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-19 | 2012-03-20 | 2012-09-19 | $7700.00 | Window Closed / Lapsed |