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US6100153A Expired / Lapsed US ⏱️ 0.0 years remaining

Reliable diffusion resistor and diffusion capacitor

Assignee: International Business Machines Corp
•
Filing: 1998-01-20
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Granted: 2000-08-08
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Expires: 2018-01-20
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Abstract

Abstract A diffusion resistor is provided that utilizes the block mask to cover only the intrinsic polysilicon gate region. The n-type source/drain doping is implanted in the contact regions, but not in the intrinsic polysilicon gate region. A N-type (or P-type) diffusion resistor in P-well (or N-well) is provided that utilizes a block mask to cover only the intrinsic polysilicon gate region. The N-type (or P-type) source/drain doping is implanted in the contact regions but not in the intrinsic polysilicon gate region. The P-well (or N-well) block mask is used to keep the P-well (or N-well) from forming under the buried resistor. This makes the parasitic capacitance of the diffusion junction very low. Also provided is a buried capacitor and method of making both a buried resistor and a buried capacitor.

Inventors

  • 👤 Edward J. Nowak
  • 👤 Xiaowei Tian
  • 👤 Minh H. Tong

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 22:49
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/025; H10D1/40; H10D1/47; H10D1/045; H10D1/047; H10D1/60; H10D1/62; H10D1/66

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 133 words
A method of forming a buried resistor comprising the steps of: providing a substrate of a first type impurity; disposing a first mask on the substrate to define a buried resistor region in the substrate; forming an isolation region in the substrate around the buried resistor region; performing a resistor formation implant having a second type impurity in the buried resistor region; disposing a second mask to block a well implant of the first type impurity from entering the buried resistor region; performing said well implant of the first type impurity; forming an insulator layer on a portion of the buried resistor region; forming a polysilicon layer on the insulator layer: disposing a blocking mask over the polysilicon layer; and implanting the second type impurity into terminal regions of the buried resistor region.
Claim 2
Independent Claim 133 words
A method of forming a buried resistor comprising the steps of: providing a substrate of a first type impurity; disposing a first mask on the substrate to define a buried resistor region in the substrate; forming an isolation region in the substrate around the buried resistor region; performing a resistor formation implant having a second type impurity in the buried resistor region; disposing a second mask to block a well implant of the first type impurity from entering the buried resistor region; performing said well implant of the first type impurity; forming an insulator layer on a portion of the buried resistor region; forming a polysilicon layer on the insulator layer: disposing a blocking mask over the polysilicon layer; and implanting the second type impurity into terminal regions of the buried resistor region.
Claim 3
Independent Claim 17 words
The method of clam 1, further comprising the step of: forming electrical contacts on the terminal regions.
Claim 4
Independent Claim 17 words
The method of clam 1, further comprising the step of: forming electrical contacts on the terminal regions.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-08-08 2004-02-07 2004-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-08-08 2008-02-07 2008-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-08-08 2012-02-07 2012-08-08 $7700.00 Window Closed / Lapsed

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