Abstract When transistors and resistors are provided on a chip or a wafer to become the electrical components of a digital or linear circuit, the emitter and collector regions must be etched simultaneously utilizing conventional photoresist techniques. In accordance with the prior art, the silicon dioxide layer over the area where the collector-contact is to be provided is substantially thicker than the silicon dioxide layer over the area where the emitter is to be provided, whereby the total time of etch must be great enough to etch the thicker silicon dioxide layer over the collector contacts, whereby the thinner layer is overetched, resulting in undercutting of the silicon dioxide layer in an umpredictable manner. The resulting emitters are larger in area than desired, resulting in a transistor having an emitter that is larger and therefore slower than is desired. A method of producing a transistor and a resistor on a chip is disclosed in which the thickness of the layers of silicon dioxide over the base and collector areas and over the resistor areas are more nearly equal prior to the emitter-collector photoresist operation, whereby overetching is greatly reduced when the holes are etched through the silicon dioxide layers in the production of the emitter and collector contacts. Furthermore, the silicon dioxide layer is grown, rather than being chemically deposited, since the grown silicon dioxide layer is denser, purer, and less likely to have pinholes therein than deposited silicon dioxide layers that have been used in the prior art.
The method as recited in claim 1 including the steps of etching a fifth opening in said third masking layer exposing a fifth area within said base prior to step (c), and then forming a heavily doped base contact region by passing impurities of said first conductivity type through said fifth opening.
Claim 2
Dependent Claim
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The method as recited in claim 2 wherein said epitaxial layer includes a second epitaxial region isolated from said first epitaxial region isolated from said first epitaxial region by said isolation region.
Claim 3
Dependent Claim
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The method as recited in claim 3 wherein a sixth opening is etched in said first masking layer concurrently with the etching of said first opening, exposing a sixth area of said second epitaxial region, and wherein said second masking layer covers said sixth area.
Claim 4
Dependent Claim
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The method as recited in claim 4 wherein step (c) further includes etching a seventh opening in said second masking layer, exposing a seventh area within said sixth area concurrently with the etching of said third and fourth openings.
Claim 5
Dependent Claim
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The method as recited in claim 5 wherein said first conductivity type is p-type and said second conductivity type is n-type.
Claim 6
Dependent Claim
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The method as recited in claim 1 wherein said second, third and fourth masking layers are thermally grown silicon dioxide.
Claim 7
Dependent Claim
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The method as recited in claim 1 wherein said body of semiconductor includes a heavily doped region of said second conductivity type extending from said buried layer through said first epitaxial region to said fourth area of said first epitaxial region, forming a low resistance path from said fourth area to said buried layer.