Process for fabricating polysilicon resistors and interconnects

Claim 1

A process for fabricating polysilicon resistors and interconnects coupled to metal-oxide-semiconductor (MOS) devices in a silicon substrate comprising the steps of: depositing a first layer of polysilicon over said substrate; selectively etching said first polysilicon layer to form the gates of said MOS devices; depositing a second layer of polysilicon between said gates; etching said second polysilicon layer so that the upper surface of said second polysilicon layer is substantially coplanar with said gates, portions of said second polysilicon layer forming source and drain contacts to said devices; forming an insulative layer over said first and second polysilicon layers; patterning said insulative layer to define contact openings to said source and drain contacts and to said gates; depositing a metal layer over said substrate, said metal layer filling said contact openings; patterning said metal layer to define electrical contacts to said source and drain contacts and to said gates, said electrical contacts being substantially coplanar with one another and acting as the terminals of said polysilicon resistors, said patterning step also defining interconnect lines in said metal layer; depositing a third layer of polysilicon over said first and second polysilicon layers; patterning said third polysilicon layer to define said polysilicon interconnects and said polysilicon resistors such that said third polysilicon layer is substantially coincident with and disposed above said interconnect lines whereever said polysilicon interconnects are formed, and extending between said electrical contacts wherever said polysilicon resistors are formed.