Patent US2158044A successfully refreshed from Google Patents.
US3700977A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Diffused resistor
Assignee: Motorola Solutions Inc
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Filing: 1971-02-17
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Granted: 1972-10-24
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Expires: 1991-02-17
Abstract
Abstract There is disclosed an improved technique for reducing or eliminating parasitic capacitance associated with diffused resistors in which the normal buried layer is eliminated and in which each resistor is either fully or partially surrounded by an isolation ring. The epitaxial layer between the resistive element and the isolation ring is provided with a back bias either at one end of the resistor or at the point along the resistor at which no signal exists. In one case this may be accomplished by shorting the epitaxial layer to the low impedance end of the resistor. In the embodiment in which one end of the resistor is shorted to the epitaxial layer, the resistor is polarized having a low impedance end and a high impedance end, such that the end to which the epitaxial layer is shorted is the end which is coupled to the low impedance node of a circuit. In the case where the resistor is to be coupled across nodes having equal impedance, the epitaxial layer is provided with back bias adjacent that point along the length of the resistor at which no signal appears. There is also disclosed a guard circuit, which minimizes parasitic capacitance in cases where a low resistivity epitaxial layer or a buried layer is provided. The guard circuit is in the form of an impedance convertor having a high impedance output applied to the high impedance end of the resistor while the low impedance of the convertor is coupled to an epitaxial layer contact adjacent this high impedance end. In the guard circuit embodiment, an additional epitaxial layer contact is provided adjacent the low impedance end of the resistor and is shorted thereto so as to provide the aforementioned back bias.
Inventors
- 👤 Gerald K Lunn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:13
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/209; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
230 words
Apparatus for reducing the effects of parasitic capacitance associated with a resistor diffused into a semiconductive material having a lower resistivity per unit length than that of said resistor comprising in combination with said resistor: means for generating a back-biasing potential at a point on said low resistivity material adjacent said resistor, said point being furthest removed from any portion of said resistor adapted to be coupled to a high impedance node of a circuit; means including semiconductive material of a conductivity type opposite to that of said low resistivity material, diffused into said low resistivity material in spaced adjacency to said resistor for isolating said resistor from any capacitance coupled path to ground outside of the area occupied by and surrounded by said isolating means; and means for deriving from the high impedance node of said circuit a high impedance signal and a low impedance replica of said high impedance signal, said high impedance signal being coupled directly to that portion of said resistor adapted to be coupled to said high impedance node, said low impedance replica being coupled to that portion of said low resistivity material adjacent the portion of said resistor adapted to be coupled to said high impedance node, whereby parasitic capacitance associated with the low resistivity of said first mentioned material is compensated for by said means for deriving said high and low impedance signals.
Claim 2
Dependent Claim
230 words
Apparatus for reducing the effects of parasitic capacitance associated with a resistor diffused into a semiconductive material having a lower resistivity per unit length than that of said resistor comprising in combination with said resistor: means for generating a back-biasing potential at a point on said low resistivity material adjacent said resistor, said point being furthest removed from any portion of said resistor adapted to be coupled to a high impedance node of a circuit; means including semiconductive material of a conductivity type opposite to that of said low resistivity material, diffused into said low resistivity material in spaced adjacency to said resistor for isolating said resistor from any capacitance coupled path to ground outside of the area occupied by and surrounded by said isolating means; and means for deriving from the high impedance node of said circuit a high impedance signal and a low impedance replica of said high impedance signal, said high impedance signal being coupled directly to that portion of said resistor adapted to be coupled to said high impedance node, said low impedance replica being coupled to that portion of said low resistivity material adjacent the portion of said resistor adapted to be coupled to said high impedance node, whereby parasitic capacitance associated with the low resistivity of said first mentioned material is compensated for by said means for deriving said high and low impedance signals.
Claim 3
Dependent Claim
211 words
Apparatus for reducing the effects of parasitic capacitance associated with a resistor diffused into a Semiconductive material having a lower resistivity per unit length than that of said resistor comprising in combination with said resistor; means for generating a back-biasing potential at a point on said low resistivity material adjacent said resistor, said point being furthest removed from any portion of said resistor adapted to be coupled to a high impedance node of a circuit; and means including semiconductive material of a conductivity type opposite to that of said low resistivity material, diffused into said low resistivity material in spaced adjacency to said resistor for isolating said resistor from any capacitance coupled path to ground outside of the area occupied by said isolating means; the high impedance node of said circuit developing a high impedance signal, said circuit having a node at which is developed a low impedance replica of said high impedance signal, the portion of said resistor adapted to be coupled to the high impedance node of said circuit adapted to be coupled to said high impedance signal, the portion of said low resistivity material adjacent the portion of said resistor adapted to be coupled to said high impedance node, adapted to be coupled to said low impedance replica.
Claim 4
Dependent Claim
211 words
Apparatus for reducing the effects of parasitic capacitance associated with a resistor diffused into a Semiconductive material having a lower resistivity per unit length than that of said resistor comprising in combination with said resistor; means for generating a back-biasing potential at a point on said low resistivity material adjacent said resistor, said point being furthest removed from any portion of said resistor adapted to be coupled to a high impedance node of a circuit; and means including semiconductive material of a conductivity type opposite to that of said low resistivity material, diffused into said low resistivity material in spaced adjacency to said resistor for isolating said resistor from any capacitance coupled path to ground outside of the area occupied by said isolating means; the high impedance node of said circuit developing a high impedance signal, said circuit having a node at which is developed a low impedance replica of said high impedance signal, the portion of said resistor adapted to be coupled to the high impedance node of said circuit adapted to be coupled to said high impedance signal, the portion of said low resistivity material adjacent the portion of said resistor adapted to be coupled to said high impedance node, adapted to be coupled to said low impedance replica.
Claim 5
Dependent Claim
107 words
The apparatus as recited in claim 2 wherein said isolating means completely surrounds said resistor, wherein said resistor has two ends, wherein a contact to said low resistivity material is provided in spaced adjacency to either end of said resistor between the ends of the resistor and said isolating means, wherein said high impedance signal is applied to one end of said resistor, wherein said low impedance replica is applied to the contact adjacent this one end, and wherein said back-biasing potential is applied to the contact adjacent the other end of said resistor, said other end being coupled to a low impedance node of said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |