Die interconnections using intermediate connection elements secured to the die face

Claim 2

A semiconductor device, comprising: a die having an active surface, having integrated circuitry, and including at least one bond pad on said active surface connected to said integrated circuitry; and at least one electrically conductive discrete jumper pad attached to said active surface of said die, said at least one jumper pad having an electrical connect portion, having a die-facing portion, and having a periphery, said at least one jumper pad being electrically isolated about its die-facing portion and its periphery.

Claim 3

The semiconductor device of claim 1, further including an insulating structure having an attachment surface attached to said die active surface and an opposed jumper pad surface carrying said at least one jumper pad.

Claim 4

The semiconductor device of claim 2, wherein said insulating structure is selected from the group comprising pressure-sensitive adhesive tape and thermosetting adhesive tape.

Claim 5

The semiconductor device of claim 2, wherein said insulating structure includes an at least partially adhesive top side.

Claim 6

The semiconductor device of claim 2, wherein said insulating structure extends over a preselected portion of said die active surface and defines at least one access hole therethrough to expose said at least one bond pad therethrough.

Claim 7

The semiconductor device of claim 1, wherein said at least one jumper pad is formed from a conductive material selected from the group comprising metals and metal alloys.

Claim 8

The semiconductor device of claim 1, further including a jumper pad adapter carrying said at least one jumper pad on a first surface thereof and attached to said die active surface by a second surface of said adapter.

Claim 9

The semiconductor device of claim 7, further including at least one conductor extending between said electrical connect portion of at least two jumper pads.

Claim 10

The semiconductor device of claim 1, further including a lead frame having at least one lead attached to said die and at least one connection between said at least one lead and said at least one bond pad being effected through an intermediate connection to said electrical connect portion of said at least one jumper pad.

Claim 11

The semiconductor device of claim 1, further including at least one wire bond between said electrical connect portion of said at least one jumper pad and said at least one bond pad.

Claim 12

The semiconductor device of claim 1, further including a printed circuit board having at least one conductive trace thereon, said die being mounted thereon and wire bonded from said electrical connect portion of said at least one jumper pad to said at least one conductive trace.

Claim 13

The semiconductor device of claim 1, further including a flex circuit having at least one conductive trace thereon, said die being mounted thereon and said electrical connect portion of said at least one jumper pad wire bonded to said at least one conductive trace.

Claim 14

The semiconductor device of claim 1, further including another die having an active surface including at least one bond pad thereon and at least one electrically isolated jumper pad, said electrical connect portion of said at least one jumper pad of said another die wire bonded to said at least one bond pad of said die.

Claim 15

The semiconductor device of claim 1, wherein said die includes functions selected from at least one of the group comprising a Dynamic Random Access Memory (DRAM) integrated circuit, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, an Electrically Erasable PROM (EEPROM) integrated circuit, a flash memory circuit, and a microprocessor circuit.

Claim 16

A semiconductor device, comprising: a first die having integrated circuitry and having an active surface including a plurality of bond pads thereon connected to at least a portion of the integrated circuitry; a plurality of discrete intermediate connection elements electrically isolated from each other, attached to said active surface of said first die and isolated from direct electrical connection with said integrated circuitry, each of said discrete intermediate connection elements having a die-facing portion, having an electrical connect portion, and having a periphery, said die-facing portion and said periphery of each discrete intermediate connection element being electrically isolated; and at least one wire bond extending from at least one of said plurality of bond pads to said electrical connect portion of at least one of said plurality of intermediate connection elements.

Claim 17

A semiconductor device, comprising: a first die having integrated circuitry and having an active surface including a plurality of bond pads thereon connected to at least a portion of the integrated circuitry; a plurality of discrete intermediate connection elements electrically isolated from each other, attached to said active surface of said first die and isolated from direct electrical connection with said integrated circuitry, each of said discrete intermediate connection elements having a die-facing portion, having an electrical connect portion, and having a periphery, said die-facing portion and said periphery of each discrete intermediate connection element being electrically isolated; and at least one wire bond extending from at least one of said plurality of bond pads to said electrical connect portion of at least one of said plurality of intermediate connection elements.

Claim 18

The semiconductor device of claim 15, further including a second die having a plurality of intermediate connection elements thereon and wherein said at least one wire bond extends from at least one of said plurality of bond pads on said first die to an electrical connect portion of at least one of said plurality of intermediate connection elements on said second die.

Claim 19

The semiconductor device of claim 15, wherein said plurality of intermediate connection elements lies entirely within a perimeter of said active surface of said first die.

Claim 20

The semiconductor device of claim 15, further including an insulating layer having an attachment side attached to said active surface of said first die and a connection element surface carrying said plurality of intermediate connection elements.

Claim 21

The semiconductor device of claim 15, further including an insulating layer carrying said plurality of intermediate connection elements and including at least one conductor connecting said electrical connect portions of at least two of said plurality of intermediate connection elements.

Claim 22

The semiconductor device of claim 15, wherein said first die includes at least one function selected from the group comprising a Dynamic Random Access Memory (DRAM) integrated circuit die, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, an Electrically Erasable PROM (EEPROM) integrated circuit, a flash memory circuit, and a microprocessor circuit.

Claim 23

A semiconductor device, comprising: a die having internal integrated circuitry and having an active surface including a plurality of bond pads thereon electrically connected to the internal integrated circuitry; a lead frame having a plurality of lead fingers located adjacent said active surface of said die; a plurality of discrete electrically conductive, mutually electrically isolated pads attached to said active surface of said die, each of said plurality of discrete electrically conductive mutuallly electrically isolated pads having an electrical connect portion, having a die-facing portion, and having a periphery, each of said plurality of discrete electrically conductive, mutually electrically isolated pads electrically isolated about its periphery and electrically isolated about its die-facing portion; at least one wire extending from at least one of said plurality of bond pads to said electrical connect portion of at least one of said plurality of discrete electrically conductive, mutually electrically isolated pads; and at least one other wire extending from at least one of said plurality of bond pads to at least one of said plurality of lead fingers.

Claim 24

A semiconductor device, comprising: a die having internal integrated circuitry and having an active surface including a plurality of bond pads thereon electrically connected to the internal integrated circuitry; a lead frame having a plurality of lead fingers located adjacent said active surface of said die; a plurality of discrete electrically conductive, mutually electrically isolated pads attached to said active surface of said die, each of said plurality of discrete electrically conductive mutuallly electrically isolated pads having an electrical connect portion, having a die-facing portion, and having a periphery, each of said plurality of discrete electrically conductive, mutually electrically isolated pads electrically isolated about its periphery and electrically isolated about its die-facing portion; at least one wire extending from at least one of said plurality of bond pads to said electrical connect portion of at least one of said plurality of discrete electrically conductive, mutually electrically isolated pads; and at least one other wire extending from at least one of said plurality of bond pads to at least one of said plurality of lead fingers.

Claim 25

The semiconductor device of claim 21, further including an insulating layer having a first surface attached to said active surface of said die and a second surface carrying said plurality of discrete electrically conductive, mutually electrically isolated pads.

Claim 26

The semiconductor device of claim 22, wherein said insulating layer includes at least one conductor extending from and electrically connected to at least one of said plurality of bond pads and electrically connected to said electrical connect portion of at least one of said plurality of discrete electrically conductive, mutually electrically isolated pads.

Claim 27

The semiconductor device of claim 21, wherein said die includes at least one function selected from the group comprising a Dynamic Random Access Memory (DRAM) integrated circuit, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, an Electrically erasable PROM (EEPROM) integrated circuit, a flash memory circuit, and a microprocessor circuit.

Claim 28

The semiconductor device of claim 21, further including an insulative encapsulant covering a portion of at least said active surface of said die.

Claim 29

A packaged semiconductor device, comprising: a die having internal integrated circuitry and having an active surface including a plurality of bond pads thereon electrically connected to a portion of the internal integrated circuitry; a lead frame having a plurality of lead fingers located adjacent said active surface of said die and extending therefrom to form external leads; a plurality of discrete conductive pads electrically isolated from each other, attached to said active surface of said die, electrically isolated from said internal circuitry of said die, each of said discrete conductive pads having an electrical connect portion, having a die-facing portion, and having a periphery, each discrete conductive pad of the plurality of discrete conductive pads electrically isolated about its die-facing portion and its periphery; at least one wire bond extending from at least one of said plurality of bond pads to said electrical connect portion of at least one of said plurality of conductive pads; at least one other wire bond extending from at least one of said plurality of bond pads to at least one of said plurality of lead fingers; and an encapsulant formed over said die.

Claim 30

A packaged semiconductor device, comprising: a die having internal integrated circuitry and having an active surface including a plurality of bond pads thereon electrically connected to a portion of the internal integrated circuitry; a lead frame having a plurality of lead fingers located adjacent said active surface of said die and extending therefrom to form external leads; a plurality of discrete conductive pads electrically isolated from each other, attached to said active surface of said die, electrically isolated from said internal circuitry of said die, each of said discrete conductive pads having an electrical connect portion, having a die-facing portion, and having a periphery, each discrete conductive pad of the plurality of discrete conductive pads electrically isolated about its die-facing portion and its periphery; at least one wire bond extending from at least one of said plurality of bond pads to said electrical connect portion of at least one of said plurality of conductive pads; at least one other wire bond extending from at least one of said plurality of bond pads to at least one of said plurality of lead fingers; and an encapsulant formed over said die.

Claim 31

The semiconductor device of claim 26, further including an insulating layer having an attachment side attached to said active surface of said die and a conductive pad surface carrying said plurality of conductive pads.

Claim 32

The semiconductor device of claim 27, wherein said insulating layer is selected from the group comprising adhesive tape and thermosetting tape.

Claim 33

The semiconductor device of claim 27, wherein said insulating layer includes an adapter carrying said plurality of discrete conductive pads on a first surface thereof and attached to said die active surface at a second surface of said adapter, said adapter comprising a first plurality of electrical contacts adjacent said second surface for connection to said plurality of bond pads, at least one conductor extending from at least one of said plurality of bond pads to at least one of said plurality of contacts.

Claim 34

The semiconductor device of claim 26, wherein said plurality of conductive pads is formed from a conductive material selected from the group comprising metals and metal alloys.

Claim 35

The semiconductor device of claim 26, wherein said die includes at least one function selected from a group comprising a Dynamic Random Access Memory (DRAM) integrated circuit, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, an Electrically Erasable PROM (EEPROM) integrated circuit, a flash memory circuit, and a microprocessor circuit.

Claim 36

A semiconductor wafer, comprising: a plurality of integrated circuit dice, each die of said plurality of integrated circuit dice having an active surface having circuitry; a plurality of bond pads on the active surface of each die of said plurality of integrated circuit dice, the plurality of bond pads on the active surface of each die electrically connected to the circuitry of its respective circuit die; and a plurality of discrete connection elements electrically isolated from each other, disposed on the active surface of each dice of said plurality of integrated circuit die electrically isolated from direct electrical connection with internal circuitry of said plurality of integrated circuit dice, each of said discrete connection elements having an electrical connect portion, a die-facing portion, and a periphery, each discrete connection element electrically isolated about its die-facing portion and about its periphery.

Claim 37

A semiconductor wafer, comprising: a plurality of integrated circuit dice, each die of said plurality of integrated circuit dice having an active surface having circuitry; a plurality of bond pads on the active surface of each die of said plurality of integrated circuit dice, the plurality of bond pads on the active surface of each die electrically connected to the circuitry of its respective circuit die; and a plurality of discrete connection elements electrically isolated from each other, disposed on the active surface of each dice of said plurality of integrated circuit die electrically isolated from direct electrical connection with internal circuitry of said plurality of integrated circuit dice, each of said discrete connection elements having an electrical connect portion, a die-facing portion, and a periphery, each discrete connection element electrically isolated about its die-facing portion and about its periphery.

Claim 38

The semiconductor wafer of claim 32, further including an insulating layer having an attachment side extending over said active surfaces of said dice and a connection element surface carrying said plurality of connection elements for said plurality of dice.

Claim 39

The semiconductor wafer of claim 33, wherein said insulating layer is selected from the group comprising a pressure-sensitive adhesive tape and thermosetting adhesive tape.

Claim 40

The semiconductor wafer of claim 32, wherein said plurality of connection elements is formed from a conductive material selected from the group comprising metals and metal alloys.

Claim 41

The semiconductor wafer of claim 32, further including a connection element adapter carrying said plurality of discreteconnection elements on a first surface thereof and attached to said each active surface of each of said plurality of dice at a second surface of said adapter, said adapter electrically connected to said plurality of bond pads of each die of said plurality of dice by a conductor extending from proximate said first surface to proximate said second surface and electrically connected to at least one of said plurality of discrete connection elements of each of said plurality of dice.

Claim 42

The semiconductor wafer of claim 32, wherein at least one of said integrated circuit dice includes at least one function selected from a group comprising a Dynamic Random Access Memory (DRAM) integrated circuit, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, an Electrically Erasable PROM (EEPROM) integrated circuit, flash memory circuit, and a microprocessor circuit.

Claim 43

A memory system comprising: a memory device including at least one semiconductor die, said at least one semiconductor die having internal circuitry having an active surface, and having a plurality of bond pads attached to said active surface electrically connected to the internal circuitry of said at least one semiconductor die; and a plurality of discrete conductive pads electrically isolated from each other attached to said active surface of said at least one semiconductor die, electrically isolated from said internal circuitry of said at least one semiconductor die, each of said discrete conductive pads having an electrical connect portion, having a die-facing portion, and having a periphery, each discrete conductive pad electrically isolated about its die-facing portion and about its periphery.

Claim 44

A memory system comprising: a memory device including at least one semiconductor die, said at least one semiconductor die having internal circuitry having an active surface, and having a plurality of bond pads attached to said active surface electrically connected to the internal circuitry of said at least one semiconductor die; and a plurality of discrete conductive pads electrically isolated from each other attached to said active surface of said at least one semiconductor die, electrically isolated from said internal circuitry of said at least one semiconductor die, each of said discrete conductive pads having an electrical connect portion, having a die-facing portion, and having a periphery, each discrete conductive pad electrically isolated about its die-facing portion and about its periphery.

Claim 45

The memory system of claim 38, further including an insulating layer having an attachment side attached to said active surface of said at least one semiconductor die and a conductive pad surface carrying said plurality of conductive pads.

Claim 46

The memory system of claim 39, wherein said insulating layer is selected from the group comprising pressure-sensitive adhesive tape and thermosetting adhesive tape.

Claim 47

The memory system of claim 39, wherein said at least one semiconductor die includes at least one function selected from a group comprising a Dynamic Random Access Memory (DRAM) integrated circuit, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, a flash memory circuit, and an Electrically Erasable PROM (EEPROM) integrated circuit.

Claim 48

The memory system of claim 38, wherein said plurality of conductive pads is formed from a conductive material selected from the group comprising metals and metal alloys.

Claim 49

The memory system of claim 38, further including a conductive pad adapter carrying said plurality of conductive pads on a first surface thereof and attached to said active surface of said at least one semiconductor die at a second surface of said adapter, said adapter electrically connected to at least one of said plurality of bond pads by a conductor extending from said at least one of said plurality of bond pads to at least one of said plurality of conductive pads.

Claim 50

An electronic system comprising: an input device; an output device; a processor device coupled to the input and output devices; and a memory device coupled to the processor device, the memory device comprising: at least one integrated circuit die having internal circuitry, having an active surface and having a plurality of bond pads attached to said active surface electrically connected to the internal circuitry of said at least one integrated circuit die; and a plurality of discrete conductive pads electrically isolated from each other, attached to said active surface of said at least one integrated circuit die electrically isolated from said internal circuitry of said at least one integrated circuit die other than through a bond pad of said plurality of bond pads, each of said discrete conductive pads having an electrical connect portion, having a die-facing portion, having a periphery, each discrete conductive pad electrically isolated about its die-facing portion and its periphery.

Claim 51

An electronic system comprising: an input device; an output device; a processor device coupled to the input and output devices; and a memory device coupled to the processor device, the memory device comprising: at least one integrated circuit die having internal circuitry, having an active surface and having a plurality of bond pads attached to said active surface electrically connected to the internal circuitry of said at least one integrated circuit die; and a plurality of discrete conductive pads electrically isolated from each other, attached to said active surface of said at least one integrated circuit die electrically isolated from said internal circuitry of said at least one integrated circuit die other than through a bond pad of said plurality of bond pads, each of said discrete conductive pads having an electrical connect portion, having a die-facing portion, having a periphery, each discrete conductive pad electrically isolated about its die-facing portion and its periphery.

Claim 52

The electronic system of claim 44, further including an insulating layer having an attachment side attached to said active surface of said at least one die and a conductive pad surface carrying said plurality of conductive pads.

Claim 53

The electronic system of claim 45, wherein said insulating layer is selected from the group comprising pressure-sensitive adhesive tape and thermosetting adhesive tape.

Claim 54

The electronic system of claim 44, wherein said plurality of conductive pads is formed from a conductive material selected from the group comprising metals and metal alloys.

Claim 55

The electronic system of claim 44, further including a conductive pad adapter carrying said plurality of conductive pads on a first surface thereof and attached to said active surface of said at least one die at a second surface of said adapter, said adapter including at least one conductor extending from at least one of said plurality of conductive pads to another of said plurality of conductive pads.

Claim 56

The electronic system of claim 44, wherein said at least one integrated circuit die includes at least one function selected from a group comprising a Dynamic Random Access Memory (DRAM) integrated circuit, a Static Random Access Memory (SRAM) integrated circuit, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit, a Programmable Read-Only Memory (PROM) integrated circuit, an Electrically Erasable PROM (EEPROM) integrated circuit, a flash memory circuit, and a microprocessor circuit.