US5255156A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bonding pad interconnection on a multiple chip module having minimum channel width
Assignee: Chartoleaux KG LLC
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Filing: 1991-09-06
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Granted: 1993-10-19
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Expires: 2011-09-06
Abstract
Abstract Disclosed is a electrical circuit (20) that includes a plurality of integrated circuits (22a,22b,22c,22d). At a distance from the perimeter (30,32) of each integrated circuit are disposed a series of spaced-apart bond pads (28). The integrated circuits are placed on a substrate material (24), such that there exists a plurality of channels (36, 38, 40) between the integrated circuits. Rows and columns of conductive traces are formed on the substrate material. Electrical connections are routed between the bond pads, preferentially using the conductive traces formed in the side channels (36, 38) that lie between the perimeter of an integrated circuit and its associated bond pads. The number of conductive traces routed in central channel (40) is minimized in order to reduce the overall area required for interconnections, thereby maximizing the area available for mounting integrated circuits on the substrate.
Inventors
- 👤 Kou-Chaun Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:05
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394; H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W90/00; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
164 words
An electrical circuit comprising: a generally planar substrate; a plurality of integrated circuits mounted on the substrate, each integrated circuit having associated with it a plurality of bond pads to which the integrated circuit is electrically coupled, the bond pads being disposed at a distance from a perimeter of the integrated circuit and arranged in a spaced-apart array, thereby defining a side channel between the perimeter of the integrated circuit and the bond pads associated with it, and defining a central channel between the bond pads associated with that integrated circuit and the bond pads associated with an adjacent integrated circuit; a plurality of conductive traces formed on the substrate, for conducting electrical signals to and from the bond pads of the integrated circuits, wherein at least a portion of the conductive traces lie in said side channels adjacent the integrated circuits, and a portion of the conductive traces lie in the central channel between the bond pads associated with the adjacent integrated circuits.
Claim 2
Dependent Claim
164 words
An electrical circuit comprising: a generally planar substrate; a plurality of integrated circuits mounted on the substrate, each integrated circuit having associated with it a plurality of bond pads to which the integrated circuit is electrically coupled, the bond pads being disposed at a distance from a perimeter of the integrated circuit and arranged in a spaced-apart array, thereby defining a side channel between the perimeter of the integrated circuit and the bond pads associated with it, and defining a central channel between the bond pads associated with that integrated circuit and the bond pads associated with an adjacent integrated circuit; a plurality of conductive traces formed on the substrate, for conducting electrical signals to and from the bond pads of the integrated circuits, wherein at least a portion of the conductive traces lie in said side channels adjacent the integrated circuits, and a portion of the conductive traces lie in the central channel between the bond pads associated with the adjacent integrated circuits.
Claim 3
Dependent Claim
55 words
The electrical circuit of claim 1, further comprising: a plurality of pins comprising electrical connection points between the bond pads and the conductive traces, said pins having a size smaller than that of a bond pad so that a pin is repositionable while continuing to maintain an electrical contact with one of the bond pads.
Claim 4
Dependent Claim
35 words
The electrical circuit of claim 1, wherein a pin in contact with a bond pad is contiguous with that bond pad and is positioned to align with and electrically connect to a selected conductive trace.
Claim 5
Dependent Claim
14 words
The electrical circuit of claim 1, wherein the conductive traces are photolithographic conductive traces.
Claim 6
Dependent Claim
66 words
The electrical circuit of claim 1, wherein a width of the central channel that lies between the bond pads of adjacent integrated circuits is minimized in order to increase the number of integrated circuits that are mounted on the substrate, by using the conductive traces disposed within the side channels to interconnect the bond pads so that fewer conductive traces within the central channel are used.
Claim 7
Dependent Claim
15 words
The electrical circuit of claim 1, wherein the integrated circuits are tape bonded integrated circuits.
Claim 8
Dependent Claim
32 words
The electrical circuit of claim 1, wherein each integrated circuit is mounted to the substrate by a plurality of fly wires that extend between the integrated circuit and its associated bond pads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-18 | 1997-04-19 | 1997-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-18 | 2001-04-19 | 2001-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-18 | 2005-04-19 | 2005-10-19 | $7700.00 | Window Closed / Lapsed |